Jose Carlos Alves Pereira Monteiro  Home/Search
Context
Related
| tahoe.inescid.pt/pt/Ficheir...1829.pdf Cached: PS.gz PS PDF This document uses CoBlitz to cache paper downloads. If your firewall is blocking outgoing connections to port 3125, you can use these links to download local copies.
Image Update HelpPS.gz PS PDF From: tahoe.inescid.pt/pt/Ficheiros... (more) (Enter author homepages) |
Rate this article:      (best)Comment on this article |
Abstract: Rapid increases in chip complexity, increasingly faster clocks, and the proliferation of portable devices have combined to make power dissipation an important design parameter. The power consumption of a digital system determines its heat dissipation as well as battery life. For some systems, power has become the most critical design constraint. (Update)
Active bibliography (related documents): More All
2.5: Power Minimization in IC Design: Principles and Applications - Pedram (1996) (Correct)
1.0: Low Power Architectural Design Methodologies - Landman (1994) (Correct)
0.7: Power Estimation and Optimization at the Logic - Level Massoud Pedram (Correct)
Similar documents based on text: More All
0.9: Model Order Reduction Techniques for Circuit Simulation - Silveira (1994) (Correct)
0.7: M 'etodos Explicitos Por Ajuste De Exponencial Para Simulacao.. - Silveira (1989) (Correct)
0.5: Supervisão de Controladores - Oliveira (1991) (Correct)
BibTeX entry: (Update)
@misc{ monteiro-computeraided,
author = "Jose Carlos Alves Pereira Monteiro",
title = "A Computer-Aided Design Methodology for Low Power Sequential Logic Circuits",
url = "citeseer.ist.psu.edu/alvespereiramonteiro96computeraided.html" }
Citations (may not include all citations):1726 Graph-Based Algorithms for Boolean Function Manipulation - Bryant - 1986
1575 Computer Architecture: a Quantitative Approach (context) - Patterson, Hennessy - 1990
717 Theory of Linear and Integer Programming (context) - Schrijver - 1987
482 Iterative Solution of Nonlinear Equations in Several Variabl.. (context) - Ortega, Rheinboldt - 1970
308 Digital Systems Testing and Testable Design (context) - Abramovici, Breuer et al. - 1990
296 Low Power CMOS Digital Design - Chandrakasan, Sheng et al. - 1992
296 Logic Minimization Algorithms for VLSI Synthesis (context) - Brayton, Hachtel et al. - 1984
181 Algebraic Decision Diagrams and their Applications - Bahar, Frohm et al. - 1993
181 Random Variables and Stochastic Processes (context) - Papoulis - 1991
161 Power Analysis of Embedded Software: A First Step Toward Sof.. - Tiwari, Malik et al. - 1994
158 Estimation of Average Switching Activity in Combinational an.. - Ghosh, Devadas et al. - 1992
151 Sequential Circuit Design Using Synthesis and Optimization (context) - Sentovich, Singh et al. - 1992
150 MIS: A Multiple-Level Logic Optimization System (context) - Brayton, Rudell et al. - 1987
148 Low-Power Digital CMOS Design (context) - Chandrakasan - 1994
114 Fast Prototyping of Datapath-Intensive Architectures (context) - Rabaey, Chu et al. - 1991
106 Optimizing Synchronous Systems (context) - Leiserson, Saxe - 1983
98 Transition Density: A New Measure of Activity in Digital Cir.. - Najm - 1993
80 On Average Power Dissipation and Random Pattern Testability .. (context) - Shen, Devadas et al. - 1992
68 Precomputation-Based Sequential Logic Optimization for Low P.. - Alidina, Monteiro et al. - 1994
65 Towards a High-Level Power Estimation Capability - Najm - 1995
62 Probabilistic Treatment of General Combinational Networks (context) - Parker, McCluskey - 1975
60 Statistical Estimation of the Switching Activity in Digital .. - Xakellis, Najm - 1994
52 HYPERLP: A System for Power Minimization Using Architectural.. (context) - Chandrakasan, Potkonjak et al. - 1992
52 Behavioral Synthesis for Low Power (context) - Raghunathan, Jha - 1994
51 Probabilistic Simulation for Reliability Analysis of CMOS VL.. - Najm, Burch et al. - 1990
51 Efficient Power Estimation for Highly Correlated Input Strea.. (context) - Marculescu, Marculescu et al. - 1995
50 Technology Decomposition and Mapping Targeting Low Power Dis.. - Tsui, Pedram et al. - 1993
49 Simultaneous Driver and Wire Sizing for Performance and Powe.. - Cong, Koh - 1994
46 Retiming and Resynthesis: Optimizing Sequential Networks wit.. (context) - Malik, Sentovich et al. - 1991
45 Estimation of Power Dissipation in CMOS Combinational Circui.. - Devadas, Keutzer et al. - 1992
43 An Exact Solution to the Transistor Sizing Problem for CMOS .. - Sapatnekar, Rao et al. - 1993
42 Retiming Sequential Circuits for Low Power - Monteiro, Devadas et al. - 1993
42 Diagnosis and Reliable Design of Digital Systems (context) - Breuer, Friedman - 1976
41 Guarded Evaluation Pushing Power Management to Logic Synthes.. - Ashar, Evaluation et al. - 1995
39 Technology Mapping for Low Power - Tiwari, Ashar et al. - 1993
38 Efficient Estimation of Dynamic Power Dissipation under a Re.. (context) - Tsui, Pedram et al. - 1993
38 IRSIM: An Incremental MOS Switch-Level Simulator (context) - Salz, Horowitz - 1989
34 Circuit Activity Based Logic Synthesis for Low Power Reliabl.. (context) - Roy, Prasad - 1993
34 Information Theoretic Measures of Energy Consumption at Regi.. (context) - Marculescu, Marculescu et al. - 1995
33 ReEncoding Sequential Circuits to Reduce Power Dissipation (context) - Hachtel, Hermida et al. - 1994
28 Low Power State Assignment Targeting Two- and Multi-level Lo.. - Tsui, Pedram et al. - 1994
27 Power Estimation in Sequential Circuits - Najm, Goel et al. - 1995
27 Estimating Dynamic Power Consumption of CMOS Circuits (context) - Cirit - 1987
25 Probabilistic Analysis of Large Finite State Machines - Hachtel, Macii et al. - 1994
24 Logic Synthesis (context) - Devadas, Ghosh et al. - 1994
24 Transformation and Synthesis of FSMs for Low Power Gated Clo.. - Benini, De Micheli - 1995
24 Multi-Level Network Optimization for Low Power (context) - Iman, Pedram - 1994
23 A High-level Language and Silicon Compiler for Digital Signa.. (context) - Hilfinger - 1985
22 Sequential Logic Synthesis (context) - Ashar, Devadas et al. - 1991
21 High-Level Synthesis Techniques for Reducing the Activity of.. - Musoll, Cortadella - 1995
21 Timed Shannon Circuits: A Power-Efficient Design Style and S.. (context) - Lavagno, McGeer et al. - 1995
21 Multi-Level Logic Minimization Using Implicit Don't Cares (context) - Bartlett, Brayton et al. - 1988
21 A Methodology for Efficient Estimation of Switching Activity.. - Monteiro, Devadas et al. - 1994
21 Scheduling Techniques to Enable Power Management - Monteiro, Devadas et al. - 1996
20 Improving the Accuracy of Circuit Activity Measurement (context) - Kapoor - 1994
19 Path-Delay-Fault Testability Properties of Multiplexor-Based.. (context) - Ashar, Devadas et al. - 1993
17 Computing the Maximum Power Cycles of a Sequential Circuit (context) - Manne, Pardo et al. - 1995
17 A Scheduling and Resource Allocation Algorithm for Hierarchi.. (context) - Potkonjak, Rabaey - 1989
16 Power Estimation for Sequential Logic Circuits - Tsui, Monteiro et al. - 1995
16 Techniques for the Power Estimation of Sequential Logic Circ.. - Monteiro, Devadas - 1995
15 Limited-Weight Codes for Low-Power I/O - Stan, Burleson - 1994
15 DelaY: An Efficient Tool for Retiming with Realistic Delay M.. - Lalgudi, Papaefthymiou - 1995
14 Low-Power State Assignment for Finite State Machines (context) - Olson, Kang - 1994
14 Improved Techniques for Estimating Signal Probabilities (context) - Krishnamurthy, Tollis - 1989
13 Decomposition of Logic Functions for Minimum Transition Acti.. (context) - Murgai, Brayton et al. - 1994
12 DAGON: Technology Mapping and Local Optimization (context) - Keutzer - 1987
11 The Boulder Optimal Logic Design System (context) - Bostick, Hachtel et al. - 1987
10 Minimization of Power in VLSI Circuits Using Transistor Sizi.. (context) - Tan, Allen - 1994
10 Synchronous Logic Synthesis: Algorithms for Cycle-Time Minim.. - De Micheli - 1991
10 Testability Measures in Pseudo-Random Testing (context) - Ercolani, Favalli et al. - 1992
10 Transistor Sizing for Minimizing Power Consumption of CMOS C.. (context) - Borah, Owens et al. - 1995
10 Technology Decomposition for Low-Power Synthesis - Panda, Najm - 1995
10 Simultaneous Scheduling and Binding for Power Minimization D.. (context) - Dasgupta, Karri - 1995
10 Switching Activity Analysis using Boolean Approximation Meth.. (context) - Uchino, Minami et al. - 1995
9 Power Dissipation Estimate by Switch Level Simulation (context) - Tjarnstrom - 1989
8 Analysis of Glitch Power Dissipation in CMOS ICs (context) - Favalli, Benini - 1995
8 A Symbolic Method to Reduce Power Consumption of Circuits Co.. - Bahar, Hachtel et al. - 1994
7 Power Estimation of Digital CMOS Circuits and the Applicatio.. (context) - Cheng - 1995
7 Optimization of Combinational and Sequential Logic Circuits .. - Monteiro, Rinderknecht et al. - 1995
6 Exact and Approximate Methods for Switching Activity Estimat.. (context) - Tsui, Pedram et al. - 1994
6 Fixed-Phase Retiming for Low Power Design - Lalgudi, Papaefthymiou - 1996
6 An Estimation Technique to Guide Low Power Resynthesis Algor.. (context) - Lennard, Newton - 1995
6 Yield Simulation for Integrated Circuits (context) - Walker - 1987
6 Determining Accuracy Bounds for SimulationBased Switching Ac.. (context) - Hill, Kang - 1995
5 LP-based Cell Selection with Constraints of Timing (context) - Tamiya, Matsunaga et al. - 1994
5 ControllabilityObservability Digital Circuit (context) - Controllability, Digital et al. - 1979
5 Electronics Research Laboratory Report (context) - Quarles, Implementation et al. - 1989
4 Low Delay-Power Product CMOS Design Using One-Hot Residue Co.. (context) - Chren - 1995
4 Computer Science Press (context) - Kohavi, Finite - 1978
4 Computing Entire Active AreaPower Consumption versu Delay Tr.. (context) - Berkelaar, the et al. - 1994
3 second edition (context) - Perry, Hill - 1994
3 Logic Restructuring for Wavepipelined Circuits (context) - Kim, Burleson et al. - 1993
3 Condition Graphs for High-Quality Behvioral Synthesis (context) - Juan, Chaiyakul et al. - 1994
2 AddisonWesley Publishing Company (context) - Weste, Eshraghian et al. - 1994
2 An Application of ADD-Based Timing Analysis to Combinational.. - Bahar, Cho et al. - 1994
2 Electromigration and Electronic Device Degradation (context) - Christou - 1994
1 A Monte Carlo Approach to Power Estimation (context) - Burch, Najm et al. - 1993
1 Logic Extraction and Factorization for Low (context) - Iman, Pedram - 1995
1 Switching Activity Estimation for Logic Circuits Using Polyn.. (context) - Monteiro, Devadas et al. - 1996
1 Black-Box Capacitance Models for Architectural Analysis (context) - Landman, Rabaey - 1994
1 Technology Mapping for Low Power Dissipation (context) - Lin - 1993
1 Register Allocation and Binding for Low (context) - Chang, Pedram - 1995
Documents on the same site (http://tahoe.inesc-id.pt/pt/Ficheiros/): More
Exact Minimization of Binary Decision Diagrams.. - Oliveira.. (1998) (Correct)
Analyzing Personal Document Spaces - Gonçalves, Jorge (Correct)
Heuristic Backtracking Algorithms for SAT - Bhalla, Lynce, de Sousa.. (Correct)
Online articles have much greater impact More about CiteSeer.IST Add search form to your site Submit documents Feedback
CiteSeer.IST - Copyright Penn State and NEC