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Abstract: this paper, we present PARLAK, a parametrized lock cache synthesizer tool. PARLAK generates a synthesizable SoCLC architecture with a user specified number of lock variables and user specified number and type(s) of processor(s). Several configurations of SoCLC hardware have been generated using PARLAK and the designs have been synthesized in Design Compiler from Synopsys. For example, PARLAK can generate a full range of customized SoCLCs, from a version for two processors with 32 lock variables ... (Update)
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BibTeX entry: (Update)
@misc{ akgul-parlak,
author = "Bilge E. S. Akgul and Vincent J. Mooney",
title = "PARLAK: Parametrized Lock Cache Synthesizer",
url = "citeseer.ist.psu.edu/akgul02parlak.html" }
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4 System-on-a-chip processor synchronization support in hardwa.. - Akgul, Mooney - 2001
4 The system-on-a-chip lock cache - Akgul, Mooney - 2002
4 Cache-based synchronization in shared memory multi-processor.. (context) - Ramachandran, Lee - 1996
4 Speculative locks for concurrent execution of critical secti.. - Martinez, Torrellas - 2001
3 A system-on-a-chip lock cache with task preemption support - Akgul, Lee et al. - 2001
2 Speculative lock elison: Enabling highly concurrent multithr.. (context) - Rajwar, Goodman - 2001
1 MIPS R4000 microprocessor users manual (2nd edition (context) - Heinrich - 1994
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