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Abstract: . Control intensive ICs pose a significant challenge to the users of formal methods in designing hardware. These ICs have to support a wide variety of requirements including synchronous and asynchronous operations, polling and interrupt-driven modes of operation, multiple concurrent threads of execution, non-trivial computational requirements, and programmability. In this paper, we illustrate the use of formal methods in the design of a control intensive IC called the "Intel 8251" Universal... (Update)
Context of citations to this paper: More
.... pipeline stage, Figure 3, and a fragment of the specification of a Universal Synchronous Asynchronous Receiver Transmitter (USART) chip [AG91b] Figure 5) side by side with our description of hopCP. In Figure 5, we have omitted many of the type and port declarations, to avoid...
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BibTeX entry: (Update)
Venkatesh Akella and Ganesh Gopalakrishnan. Specification and validation of control intensive ics in hopcp. Technical Report UUCS-92-001, Dept. of Computer Science, University of Utah, Salt Lake City, UT 84112, 1991. Submitted to the IEEE Transactions on Software Engineering. http://citeseer.ist.psu.edu/akella94specification.html More
@article{ akella94specification,
author = "Venkatesh Akella and Ganesh Gopalakrishnan",
title = "Specification and Validation of Control-Intensive {IC}'s in {hopCP}",
journal = "Software Engineering",
volume = "20",
number = "6",
pages = "405-423",
year = "1994",
url = "citeseer.ist.psu.edu/akella94specification.html" }
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