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Abstract: Asynchronous/self-timed designs are beginning to attract attention as promising means of dealing with the complexity of modern VLSI technology. They are characterized by absence of global clocking and concurrency limited only by the data and control dependencies. They offer the advantages of simpler timing, the absence of clock distribution related problems, composability, opportunities for incremental improvement, and robustness. This dissertation addresses the issues underlying automating... (Update)
Context of citations to this paper: More
...la nature des donn ees, etc. Mais jusqu a pr esent, peu d outils int egr es a des environements CAO (par exemple l outil d ecrit dans [2]) existent et sont utilis es pour la conception de haut niveau de ces architectures. Dans la suite on va pr esenter une approche qui...
...la nature des donn ees, etc. Mais jusqu a pr esent, peu d outils int egr es a des environements CAO (par exemple l outil d ecrit dans [2]) existent et sont utilis es pour la conception de haut niveau de ces architectures. Dans le domaine des langages synchrones, une approche...
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Flow Analysis Techniques in High Level Asynchronous.. - Akella, Gopalakrishnan (Correct)
Vers la synth`ese automatique de circuits `a partir de.. - Krzysztof Wolinski.. (Correct)
Vers La Synthèse Automatique De Programmes Signal - Wolinski, Belhadj (1993) (Correct)
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2.0: SHILPA: A High-Level Synthesis System for Self-timed Circuits - Akella, Gopalakrishnan (1992) (Correct)
0.7: Specification and Validation of Control Intensive ICs in hopCP - Akella, Gopalakrishnan (1994) (Correct)
0.6: A Transformational Approach To Asynchronous High-Level.. - Ganesh Gopalakrishnan.. (1993) (Correct)
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0.3: Performance Analysis of Mixed Asynchronous Synchronous.. - Teich, Sriram, Thiele.. (1994) (Correct)
0.2: A Cell Set for Self-Timed Design Using Xilinx XC4000 Series.. - Kapilan Maheswaran (1994) (Correct)
0.2: Fault-Tolerant Hierarchical Networks for Shared Memory .. - Mahmud, Samaratunga.. (2002) (Correct)
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BibTeX entry: (Update)
Venkatesh Akella. An integrated framework for high level synthesis of self-timed circuits. PhD thesis, University of Utah, dec 1992. http://citeseer.ist.psu.edu/akella92integrated.html More
@phdthesis{ akellaakellaintegrated,
author = "Venkatesh Akella",
title = "An Integrated Framework for High-level Synthesis of Self-timed Circuits",
url = "citeseer.ist.psu.edu/akella92integrated.html" }
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Documents on the same site (http://www.ece.ucdavis.edu/cerl/asrg.html): More
SHILPA: A High-Level Synthesis System for Self-timed Circuits - Akella, Gopalakrishnan (1992) (Correct)
Hazard-Free Implementation of the Self-Timed Cell Set in a.. - Maheswaran, Akella (1994) (Correct)
Flow Analysis Techniques in High Level Asynchronous.. - Akella, Gopalakrishnan (Correct)
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