(Enter summary)
Abstract: The compare and branch sequences required in a traditional
sort algorithm can not efficiently exploit multiple execution
units present in currently available high performance RISC
processors. This is because of the long latency of the
compare instructions and the sequential algorithm used in
sorting. With the increased level of integration on a chip,
this trend is expected to continue. We have developed new
sort algorithms which eliminate almost all the compares,
provide functional parallelism... (Update)
Context of citations to this paper: More
...created, most of its records are resident in main memory. Also since the sorting process continuously operates on a group of elements [34], there is a perceptible amount of cache to cache data transfers in the shared memory configurations. Query Q3 performs two join...
...of I O and computation during parallel disks merging of arbitrary runs. There are many good practical implementations of sorting (e.g. [19, 1, 30, 20]) that address parallel disks, overlapping of I O and computation, and low internal overhead. However, we are not aware of fast...
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BibTeX entry: (Update)
R. Agarwal. A super scalar sort algorithm for RISC processors. In Proceedings of 1996 ACM SIGMOD International Conference on Management of Data, pages 240--6, 1996. http://citeseer.ist.psu.edu/agarwal96super.html More
@inproceedings{ agarwal96super,
author = "Ramesh C. Agarwal",
title = "A super scalar sort algorithm for {RISC} processors",
pages = "240--246",
year = "1996",
url = "citeseer.ist.psu.edu/agarwal96super.html" }
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AlphaSort: A Cache Sensitive Parallel External Sort
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A Scalable Parallel Implementation of the NAS Integer Sort B.. (context) - Agarwal, Gustavson et al. - 1994
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SGI Media Brief dated May (context) - Brief, May - 1995
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