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Abstract: This paper is primarily concerned with the programmer's model of a shared memory system and its implications on hardware design and performance. A model for correct behavior of programs commonly (and often implicitly) assumed by programmers is that of sequential consistency, formally defined by Lamport [Lam79] as follows: [A system is sequentially consistent if] the result of any execution is the same as if the operations of all the processors were executed in some sequential order, and the... (Update)
Context of citations to this paper: More
...which offer weaker consistency properties have been proposed. These advanced protocols are based on the concept of weak ordering [1], and coherency protocols based on weak ordering offer performance improvements by allowing invalidations generated by a thread whilst...
...performance beyond five Instructions Per Cycle (IPC) A weak ordering programmer s model offers greater performance potential. Adve and Hill [1989] state A system is weakly ordered with respect to a synchronization model if and only if it appears sequentially consistent to...
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BibTeX entry: (Update)
S. V. ADVE and M. D. HILL, Weak Ordering - A New Definition And Some Implications, Computer Sciences Technical Report #902, University of Wisconsin, Madison, December 1989. http://citeseer.ist.psu.edu/adve89weak.html More
@techreport{ adve89weak,
author = "Sarita V. Adve and Mark D. Hill",
title = "Weak Ordering - {A} New Definition and Some Implications",
number = "CS-TR-1989-902",
year = "1989",
url = "citeseer.ist.psu.edu/adve89weak.html" }
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606 How to Make a Multiprocessor Computer That Correctly Execute.. (context) - Lamport - 1979
159 The NYU Ultracomputer--Designing an MIMD Shared Memory Paral.. (context) - Gottlieb, Grishman et al. - 1983
156 An Evaluation of Directory Schemes for Cache Coherence - Agarwal, Simoni et al. - 1988
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148 A Fast Mutual Exclusion Algorithm - Lamport - 1987
137 Lockup-Free Instruction Fetch/Prefetch Cache Organization (context) - Kroft - 1981
112 Efficient Synchronization Primitives for Large-Scale Cache-C.. (context) - Goodman, Vernon et al. - 1989
90 The IBM Research Parallel Processor Prototype (context) - Pfister, Brantley et al. - 1985
81 Implementing Precise Interrupts in Pipelined Processors (context) - Smith, Pleszkun - 1988
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70 Dynamic Decentralized Cache Schemes for MIMD Parallel Proces.. (context) - Rudolph, Segall - 1984
57 Reasoning about Parallel Architectures (context) - Collier - 1990
57 Reasoning about Parallel Architectures (context) - Collier - 1985
52 Parts I and II (context) - Lamport, Communication - 1986
48 and Event Ordering in Multiprocessors (context) - Dubois, Scheurich et al. - 1988
40 Correct Memory Operation of Cache-Based Multiprocessors (context) - Scheurich, Dubois - 1987
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21 Parallel Execution of Sequential Scheme with ParaTran (context) - Tinker, Katz - 1988
20 Detecting Data Races in Parallel Program Executions - Netzer, Miller - 1989
17 The Mutual Exclusion Problem (context) - Lamport - 1986
15 Concurrent Miss Resolution in Multiprocessor Caches (context) - Scheurich, Dubois - 1988
15 Access Ordering and Coherence in Shared Memory Multiprocesso.. (context) - Scheurich - 1989
13 Coherent Shared Memory on a Distributed Memory Machine (context) - Bisiani, Nowatzyk et al. - 1989
11 Model 91: Machine Philosophy and Instruction-Handling (context) - Anderson, Sparacio et al. - 1967
5 RP3 Process-Memory Element (context) - Brantley, McAuliffe et al. - 1985
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3 Architectures for Systems of Parallel Processes (context) - Collier - 1984
3 Thirteenth Annual International Symposium on Computer Archit.. (context) - Dubois, Scheurich et al. - 1986
1 Write Atomicity in Distributed Systems (context) - Collier - 1984
1 Levels of Ordering and Consistency in Shared-Memory Multipro.. (context) - Nicholas - 1989
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