Santosh G. Abraham, Vinod Kathail, Brian L. Deitrich  Home/Search
Context Related
| hp.com/research/itc/car/pape...Meld.pdf Cached: PS.gz PS PDF This document uses CoBlitz to cache paper downloads. If your firewall is blocking outgoing connections to port 3125, you can use these links to download local copies.
Image Update HelpPS.gz PS PDF From: hp.com/research/itc/car/papers... (more) (Enter author homepages) |
Rate this article:      (best)Comment on this article |
Abstract: Meld scheduling melds the schedules of neighboring scheduling regions to respect latencies of operations issued in one region but completing after control transfers to the other. In contrast, conventional schedulers ignore latency constraints from other regions leading to potentially avoidable stalls in an interlocked (superscalar) machine or incorrect schedules for non-interlocked (VLIW) machines. Alternatively, schedulers that conservatively require all operations to complete before the... (Update)
Context of citations to this paper: More
...( 94) 1.20 (1.56) 211L3 1.02 (1.02) 1.07 (1.23) 0.95 ( 97) 1.04 (1. 09) allowing latency constraints to propagate outside the scheduling region [18]. Programs spend a significant fraction of the total execution time in loops and special scheduling techniques have been developed...
Cited by: More
Trimaran: An Infrastructure for Research in - Instruction-Level Parallelism.. (Correct)
Efficient Backtracking Instruction Schedulers - Abraham (2000) (Correct)
Active bibliography (related documents): More All
0.5: Memory Disambiguation To Facilitate Instruction-Level.. - Gallagher (1995) (Correct)
0.0: Modulo Scheduling With Isomorphic Control Transformations - Warter (1994) (Correct)
0.0: Compilers for Instruction-Level Parallelism - Schlansker, al. (1997) (Correct)
System load high. Please wait...
Timeout. Please try your query later.
Similar documents based on text: More All
0.3: Randomized Meldable Priority Queues - Gambin, Malinowski (Correct)
0.3: A Tight Lower Bound for Top-Down Skew Heaps - Schoenmakers (1997) (Correct)
0.3: Meta Optimization: Improving Compiler Heuristics.. - Stephenson.. (2002) (Correct)
Related documents from co-citation: More All
6: Iterative Modulo Scheduling (context) - Rau - 1996
4: EPIC: Explicitly Parallel Instruction Computing - Schlansker, Rau - 2000
4: Instruction-level parallel processing: History (context) - Rau, Fisher - 1993
BibTeX entry: (Update)
S.G. Abraham, V. Kathail, and B.L. Dietrich, "Meld scheduling: A technique for relaxing scheduling constraints," Int. J. Parallel Programming, vol. 26, no. 4, pp. 349-381, 1998 (techical report version at http://www.hpl.hp.com/techreports/97/HPL -97-39.html). http://citeseer.ist.psu.edu/abraham98meld.html More
@article{ abraham98meld,
author = "Santosh G. Abraham and Vinod Kathail and Brian L. Deitrich",
title = "Meld Scheduling: A Technique for Relaxing Scheduling Constraints",
journal = "International Journal of Parallel Programming",
volume = "26",
number = "4",
pages = "349--381",
year = "1998",
url = "citeseer.ist.psu.edu/abraham98meld.html" }
Citations (may not include all citations):452 Data Structures and Algorithms (context) - Aho, Hopcroft et al. - 1983
407 Trace scheduling: A technique for global microcode compactio.. (context) - Fisher - 1981
353 Software pipelining: an effective scheduling technique for V.. (context) - Lam - 1988
176 Some scheduling techniques and an easily schedulable horizon.. (context) - Rau, Glaeser - 1981
173 Bulldog: A Compiler for VLIW Architectures (context) - Ellis - 1985
164 The superblock: an effective technique for VLIW and supersca.. (context) - Hwu, Mahlke et al. - 1993
158 Effective compiler support for predicated execution using th.. - Mahlke, Lin et al. - 1992
156 The Multiflow Trace Scheduling Compiler - Lowney, Freudenberger et al. - 1993
150 Iterative modulo scheduling: an algorithm for software pipel.. - Rau - 1994
107 Global instruction scheduling for superscalar machines (context) - Bernstein, Rodeh - 1991
98 HPL PlayDoh architecture specification: Version 1.0 (context) - Kathail, Schlansker et al. - 1993
62 An efficient resource-constrained global scheduling techniqu.. (context) - Moon, Ebcioglu - 1992
35 Percolation scheduling: a parallel compilation technique (context) - Nicolau - 1985
24 Compiling for the Cydra 5 (context) - Dehnert, Towle - 1993
2 Unrolling-based optimizations for software pipelining (context) - Lavery, Hwu - 1995
1 Implementation of Global Scheduling (context) - Srivastava - 1988
Documents on the same site (http://www.hpl.hp.com/research/itc/car/papers/): More
Code Size Minimization and Retargetable Assembly for custom .. - Aditya, Mahlke, Rau (2000) (Correct)
Automatic architectural synthesis of VLIW and EPIC processors - Aditya, Rau, Kathail (Correct)
Parallelization of Control Recurrences for ILP Processors - Schlansker, Kathail, Anik (1994) (Correct)
Online articles have much greater impact More about CiteSeer.IST Add search form to your site Submit documents Feedback
CiteSeer.IST - Copyright Penn State and NEC