Evaluation of a low-power reconfigurable DSP architecture (1998) [14 citations — 0 self]
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by Arthur Abnous, Katsunori Senoy, Marlene Wan, Jan Rabaey
proceedings 5 th Reconfigurable Architectures workshop (RAW’98), March 30
http://ipdps.eece.unm.edu/1998/raw/abnous.pdf
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@INPROCEEDINGS{Abnous98evaluationof,author = {Arthur Abnous and Katsunori Senoy and Marlene Wan and Jan Rabaey},
title = {Evaluation of a low-power reconfigurable DSP architecture},
booktitle = {proceedings 5 th Reconfigurable Architectures workshop (RAW’98), March 30},
year = {1998},
pages = {55--60},
publisher = {Springer}
}
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Abstract:
Abstract. Programmability is an important capability that provides flexible computing devices, but it incurs significant performance and power penalties. We have proposed an architecture that relies on dynamic reconfiguration of hardware resources to implement low-power and programmable processors for DSP applications. In this paper, we evaluate this architectural approach and compare it to other programmable architectures. 1
Citations
| 50 | et al., “A 160-MHz, 32-b, 0.5-W CMOS RISC Microprocessor – Montanaro - 1996 |
| 15 | et al., “Fast Prototyping of DatapathIntensive Architectures – Rabaey - 1991 |
| 3 | Calculation of TMS320LC54x Power Dissipation – Turner - 1997 |
| 3 | Calculation of TMS320C2xx Power Dissipation – Turner - 1996 |
| 2 | The TMS320C2xx Sum-of-Products Methodology – Anderson - 1996 |
| 1 | Designing Low-Power Applications with the TMS320LC54x, Technical Application Report SPRA281, Texas Instruments – Fischman, Rowland - 1997 |
