This directory is created automatically and some papers may be mislabeled. Only document within the CiteSeer database are listed. The directory is intended to provide entry points for browsing the database and is not intended to be authoritative. Papers may not appear in all relevant categories. For example, papers in a sub-category may not appear in higher level categories.
1150.5 RSVP: A New Resource ReSerVation Protocol - Zhang, Deering, Estrin, Shenker.. (1993)(Correct)
this article we describe another. unknown RSVP: A New Resource ReSerVation Protocol
Lixia Zhang
, Steve Deering
, Deborah Estrin
, Scott Shenker
, Daniel Zappala
flixia, deering, shenkerg@parc.xer... / signal while those receivers with hardware decoding or more processing
693.6 CORBA: Integrating Diverse Applications Within Distributed.. - Vinoski (1997)(Correct)
This paper will appear in the feature topic issue of the IEEE Communications Magazine, Vol. 14, No. 2, February 1997. It is presented in this format to ensure timely dissemination of scholarly and tec... / us to use the best combination of hardware and software components for each br the operating system if any and hardware it executes on. ffl Object
594.0 PVM: A Framework for Parallel Distributed Computing - Sunderam (1990)(Correct)
The PVM system is a programming environment for the development and
execution of large concurrent or parallel applications that consist of many
interacting, but relatively independent, components. It ... / environments already possess the hardware diversity required to solve such br them on the most appropriate hardware available either directly or by
557.4 System Design Issues for Internet Middleware Services: Deductions.. - Gribble (1997)(Correct)
System Design Issues for Internet Middleware Services: Deductions from a Large
Client Trace
by
Steven D. Gribble
Master of Science in Computer Science
University of California at Berkeley
Professor Er... / population with wide variation in hardware software and network br more powerful Pentium Pro MHz hardware that we used to collect the
540.7 The NAS Parallel Benchmarks - Bailey, Barszcz, Barton, Browning.. (1994)(Correct)
A new set of benchmarks has been developed for the performance
evaluation of highly parallel supercomputers. These benchmarks consist
of five "parallel kernel" benchmarks and three "simulated applicat... / not kept pace with advances in hardware software and algorithms. In br term processor is defined as a hardware unit capable of integer and
534.0 Efficient Software-Based Fault Isolation - Wahbe, Lucco, Anderson, Graham (1993)(Correct)
One way to provide fault isolation among cooperating software modules is to place each in its own address space. However, for tightly-coupled modules, this solution incurs prohibitive context switch o... / poses a tradeoff relative to hardware fault isolation substantially br isolation in software rather than hardware can substantially improve
485.1 Effective Erasure Codes for Reliable Computer Communication Protocols - Rizzo (1997)(Correct)
Reliable communication protocols require that all the intended recipients of a message receive the message intact. Automatic Repeat reQuest (ARQ) techniques are used in unicast protocols, but they do ... / with properly designed and working hardware or more frequently from br bits and implemented on dedicated hardware in the latter erasure codes are
478.2 Multiscalar Processors - Sohi (1995)(Correct)
Multiscalar processors use a new, aggressive implementation
paradigm for extracting large quantities of instruction
level parallelism from ordinary high level language programs.
A single program is di... / by a combination of software and hardware. The tasks are distributed to a br of multiscalar programs and the hardware architecture of a multiscalar
472.3 Cluster-Based Scalable Network Services - Fox, Gribble, Chawathe, Brewer.. (1997)(Correct)
This paper has benefited from the detailed and perceptive comments of our reviewers, especially our shepherd Hank Levy. We thank Randy Katz and Eric Anderson for their detailed readings of early draft... / and linear increase in hardware can maintain the same per-user br x despite transient partial hardware or software failures. By
469.5 Performance of Various Computers Using Standard Linear Equations.. - Dongarra (1995)(Correct)
This report compares the performance of different computer systems in solving dense systems of linear equations. The comparison involves approximately a hundred computers, ranging from a Cray Y-MP to ... / as new machines are added and as hardware and software systems improve. br no attempt was made to use special hardware features or to exploit vector
457.9 Intelligent Agents: Theory and Practice - Wooldridge, Jennings (1995)(Correct)
The concept of an agent has become important in both Artificial Intelligence (AI) and mainstream computer science. Our aim in this paper is to point the reader at what we perceive to be the most impor... / problem of designing software or hardware systems that will satisfy the br term agent is used is to denote a hardware or more usually software-based
449.2 Measurement-based Admission Control Algorithms for Controlled-load.. - Jamin, al. (1995)(Correct)
The Internet Engineering Task Force (IETF) is considering the adoption of the controlled-load service, a real-time service with very relaxed service guarantees [Wro95]. Measurement-based admission con... / and their implementations in hardware DJM C WCKG br the load sampling mechanism in hardware allowing users to set the
439.6 Foundations for the Study of Software Architecture - Perry, Wolf (1992)(Correct)
The purpose of this paper is to build the foundation for software architecture. We first develop an intuition for software architecture by appealing to several wellestablished architectural discipline... / disciplines such as hardware network and building br software architecture. We look at hardware and network architecture because
374.1 Lazy Release Consistency for Software Distributed Shared Memory - Keleher, Cox, Zwaenepoel (1992)(Correct)
Relaxed memory consistency models, such as release consistency, were introduced in order to reduce the impact of remote memory access latency in both software and hardware distributed shared memory (D... / latency in both software and hardware distributed shared memory DSM br the past few years researchers in hardware distributed shared memory DSM
365.2 Value Locality and Load Value Prediction - Lipasti, al. (1996)(Correct)
Since the introduction of virtual memory demand-paging
and cache memories, computer systems have been exploiting
spatial and temporal locality to reduce the average latency of a
memory reference. In t... / caches Jou and sophisticated hardware prefetching CB to alleviate br the capabilities of the cache hardware. Such improvements have primarily
361.7 Infomaster: An Information Integration System - Genesereth, Keller, Duschka (1997)(Correct)
Infomaster is an information integration system that provides
integrated access to multiple distributed heterogeneous
information sources on the Internet, thus giving the illusion
of a centralized, ho... / that all databases use a standard hardware and software platform language
358.6 Transis: A Communication Sub-System for High Availability - Yair Amir (1992)(Correct)
This paper describes Transis, a communication subsystem
for high availability. Transis is a transport
layer that supports reliable multicast services. The
main novelty is in the efficient implementati... / the characteristics of available hardware. The underlying model consists of br to a LAN. The model assumes hardware and software support for
358.0 The Network Architecture of the Connection Machine CM-5 - Leiserson, Abuhamdeh, Douglas.. (1994)(Correct)
The Connection Machine Model CM-5 Supercomputer is a massively parallel computer system designed to offer performance in
the range of 1 teraflops (10
12
floating-point operations per second). The CM... / back-door access to all system hardware to test system integrity and to br figures for the latest hardware release. The CM- Network
357.4 Application Performance and Flexibility on Exokernel Systems - Kaashoek, Engler, Ganger.. (1997)(Correct)
The exokernel operating system architecture safely gives untrusted
software efficient control over hardware and software resources by
separating management from protection. This paper describes an
exo... / software efficient control over hardware and software resources by br UNIX systems running on the same hardware using large real-world
356.5 The Nexus Approach to Integrating Multithreading and Communication - Foster (1996)(Correct)
Lightweight threads have an important role to play in parallel systems: they can be used to exploit shared-memory parallelism, to mask communication and I/O latencies, to implement remote memory acces... / efficiently on commodity hardware and software systems. br may be performed by specialized hardware e.g.remote memory put get
353.6 The Transis Approach to High Availability Cluster Communication - Dolev (1996)(Correct)
Introduction
In the local elections system of the municipality of "Wiredville"
1
, several computers were used to
establish an electronic town hall. The computers were linked by a network. When an ... / messages using selective hardware-multicast. Coupled with a br of communicating via broadcast hardware or via selective-multicast
323.4 Extensible Security Architectures for Java - Wallach (1997)(Correct)
Mobile code technologies such as Java, JavaScript, and ActiveX generally limit all programs to a single security policy. However, software-based protection can allow for more flexible security models,... / improvements over traditional hardware-based solutions. We describe and br levels have been implemented in hardware memory protection via base
310.1 An Application Level Video Gateway - Amir, McCanne, Zhang (1995)(Correct)
The current model for multicast transmission of video over
the Internet assumes that a fixed average bandwidth is
uniformly present throughout the network. Consequently,
sources limit their transmissi... / processing power and video audio hardware configurations. One host may be a br workstation without special video hardware another host may be a PC with a
306.3 Secrecy by Typing in Security Protocols - Abadi (1997)(Correct)
We develop principles and rules for achieving secrecy properties in security protocols. Our approach is based on traditional classification techniques, and extends those techniques to handle concurr... / that controls all the hardware in the system may hope to br is mediated by the system hardware the control of all information
301.4 Making Paths Explicit in the Scout Operating System - Mosberger, Peterson (1996)(Correct)
This paper makes a case for paths as an explicit abstraction
in operating system design. Paths provide a unifying
infrastructure for several OS mechanisms that have
been introduced in the last several... / domains systems often impose hardware-enforced protection at layer br separate fault domain. Similarly hardware-enforced protection could be
296.9 A Methodology for Implementing Highly Concurrent Data Objects - Herlihy (1993)(Correct)
A concurrent object is a data structure shared by concurrent processes.
Conventional techniques for implementing concurrent objects typically rely
on critical sections: ensuring that only one process ... / is less efficient than direct hardware support. For example a br can be checked either by hardware or by software. A simple hardware
281.0 Authentication in Distributed Systems: Theory and Practice - Lampson, Abadi, Burrows, Wobber (1992)(Correct)
this paper appeared in the Proceedings of the Thirteenth ACM Sympos - ium on Operating Systems Principles. unknown Lampson et al, Authentication in Distributed Systems 1
A preliminary version of / based on encryption and the hardware and local operating system on br a small amount of software and hardware that security depends on and that
276.5 Baring it all to software: Raw machines - Waingold, al. (1997)(Correct)
this article. This project is funded by US Defense Advanced Research Projects Agency contract DABT63-96-C-0036 and a National Science Foundation Presidential Young Investigator Award. Ikos Systems don... / that fully exposes the hardware architecture's low-level details br a minimal set of mechanisms in hardware. Raw machines require only short
275.3 Adapting to Network and Client Variability via On-Demand Dynamic.. - Fox (1996)(Correct)
this paper we introduce some design principles that we believe are fundamental to providing "meaningful " Internet access for the entire range of clients. In particular, we show how to perform on-dema... / clients. Clients vary in their hardware resources software br important dimensions network hardware and software. Network
257.9 An Event-Based Architecture Definition Language - Luckham, Vera (1995)(Correct)
This paper discusses general requirements for
architecture definition languages, and describes the syntax
and semantics of the subset of the Rapide language that is designed
to satisfy these requireme... / and distributed systems both hardware and software. In order to br examples from both software and hardware. Also we give a detailed example
249.3 Fine-grain Access Control for Distributed Shared Memory - Schoinas (1994)(Correct)
This paper discusses implementations of fine-grain memory
access control, which selectively restricts reads and
writes to cache-block-sized memory regions. Fine-grain
access control forms the basis of... / require little or no additional hardware. These techniques permit br that require no additional hardware into Blizzard a system that
243.2 The Zebra Striped Network File System - Hartman, Ousterhout (1993)(Correct)
Zebra is a network file system that increases throughput by striping file data across multiple servers. Rather than striping each file separately, Zebra forms all the new data from each client into a ... / Sprite file system on the same hardware. For small files the Zebra br operation in the event of a hardware failure. Zebra borrows its log
242.5 Scalable High Speed IP Routing Lookups - Waldvogel, Varghese, Turner, Plattner (1997)(Correct)
Internet address lookup is a challenging problem because of increasing routing table sizes, increased traffic, higher speed links, and the migration to 128 bit IPv6 addresses. IP routing lookup requir... / schemes trie based schemes hardware solutions based on parallelism br large storage requirements. Hardware Solutions Hardware solutions can
239.1 Comparing Images Using the Hausdorff Distance - Huttenlocher, Klanderman, Rucklidge (1993)(Correct)
The Hausdorff distance measures the extent to which each point of a `model' set lies near some point of an `image' set and vice versa. Thus this distance can be used to determine the degree of resembl... / up using special-purpose graphics hardware in particular a z-buffer We br advantage of specialized graphics hardware for rendering and z-buffering.
236.7 The MIT Alewife Machine: A Large-Scale Distributed-Memory.. - Agarwal, Chaiken, Johnson, Kranz.. (1991)(Correct)
The Alewife multiprocessor project focuses on the architecture and design of a large-scale parallel machine. The machine uses a low dimension direct interconnection network to provide scalable communi... / and concentrates on the novel hardware features of the machine including br The compiler runtime system and hardware cooperate to enhance
234.5 Scheduling for Reduced CPU Energy - Weiser, Welch, Demers, Shenker (1994)(Correct)
The energy usage of computer systems is becoming
more important, especially for battery operated
systems. Displays, disks, and cpus, in that order, use
the most energy. Reducing the energy used by dis... / require experiments with real hardware. Trace data was taken from UNIX br Michael Culbert Low Power Hardware for a High Performance PDA to
226.0 Optimizing Power Using Transformations - Chandrakasan, Potkonjak, Mehra.. (1995)(Correct)
The increasing demand for portable computing has elevated power consumption to be one of the most critical design parameters. A high-level synthesis system, HYPER-LP, is presented for minimizing pow... / at reduced supply voltages through hardware duplication or pipelining. By br to reduce the required amount of hardware while preserving the number of
220.3 Weak Ordering - A New Definition - Adve (1990)(Correct)
A memory model for a shared memory, multiprocessor
commonly and often implicitly assumed by programmers
is that of sequential consistency. This model
guarantees that all memory accesses will appear to... / in terms of a set of rules for hardware that have to be made visible to br a contract between software and hardware. By this contract software
218.1 The Jalapeño Dynamic Optimizing Compiler for Java - Burke, Choi, Fink, Grove, Hind.. (1999)(Correct)
The Jalape~no Dynamic Optimizing Compiler is a key component of the Jalape~no Virtual Machine, a new Java 1 Virtual Machine (JVM) designed to support efficient and scalable execution of Java applicati... / Compiler to a variety of hardware platforms. Building a dynamic br combined with a collection of hardware performance monitor information
217.0 Visibility Culling Using Hierarchical Occlusion Maps - Zhang, Manocha, Hudson, Hoff, III (1997)(Correct)
We present hierarchical occlusion maps (HOM) for
visibility culling on complex models with high depth complexity.
The culling algorithm uses an object space bounding volume hierarchy
and a hierarchy... / be accelerated by texture mapping hardware. It is not susceptible to br the Z-pyramid capability in hardware and simulating it in software
214.3 Munin: Distributed Shared Memory Based on Type-Specific Memory.. - Bennett, Carter, Zwaenepoel (1990)(Correct)
We are developing Munin, a system that allows programs written for shared memory multiprocessors to be executed efficiently on distributed memory machines. Munin attempts to overcome the architectural... / similar to that provided by hardware cache coherence mechanisms on br of sharing than are possible in hardware. In particular it allows us to
209.0 A Fast Bit-Vector Algorithm for Approximate String Matching Based on.. - Gene Myers (1999)(Correct)
The approximate string matching problem is to find all locations at which a query of length
m matches a substring of a text of length n with k-or-fewer differences. Simple and practical bitvector
alg... / results exploited the hardware parallelism of bit-vector br in the instruction pipeline hardware. Figure depicts the values of
205.7 Memory Bandwidth Limitations of Future Microprocessors - Burger (1996)(Correct)
This paper makes the case that pin bandwidth will be a critical consideration for future microprocessors. We show that many of the techniques used to tolerate growing memory latencies do so at the exp... / load scheduling hardware and software prefetching br load scheduling Hardware prefetching Software
195.0 Scout: A Communications-Oriented Operating System - Montz, Mosberger, O'Malley.. (1994)(Correct)
This white paper describes Scout, a new operating system being designed for systems connected to the National Information Infrastructure (NII). Scout provides a communication-oriented software archite... / is to either build specialized hardware which is generally not a br operating systems have changed hardware has changed and compiler
194.2 Evolution of Homing Navigation in a Real Mobile Robot - Floreano, Mondada (1996)(Correct)
In this paper we describe the evolution of a discrete-time recurrent neural network to control a real mobile robot. In all our experiments the evolutionary procedure is carried out entirely on the phy... / be easily added thanks to the hardware and software modularity of the br charger rather than using the hardware available is time. Considering
194.2 Scope Consistency : A Bridge between Release Consistency and Entry.. - Liviu Iftode (1996)(Correct)
Systems that maintain coherence at large granularity such as
shared virtual memory systems, suffer from false sharing and
extra communication. Relaxed memory consistency models
have been used to allev... / two ScC protocols one that uses hardware support for fine-grained remote br network interfaces that provide hardware support for word-level automatic
194.2 Visual Navigation of Large Environments Using Textured Clusters - Maciel, Shirley (1995)(Correct)
A visual navigation system is described which uses texture
mapped primitives to represent clusters of objects to maintain
high and approximately constant frame rates. In cases
where there are more uno... / approaches to this problem use a hardware graphics pipeline and attempt to br primitives than state-of-the-art hardware can render in real-time even if
188.4 Charlotte: Metacomputing on the Web - Baratloo (1996)(Correct)
The World Wide Web has the potential of being used as
an inexpensive and convenient metacomputing resource.
This brings forward new challenges and invalidates many
of the assumptions made in offering ... / system is required local hardware is protected from programs br Web contains different types of hardware running different operating
188.4 The STATEMATE Semantics of Statecharts - Harel, Naamad (1996)(Correct)
We describe the semantics of statecharts as implemented in the Statemate system. This
was the first executable semantics defined for the language, and has been in use for almost a
decade. In terms of ... / of models and to generate useful hardware and software code out of these br language for the description of hardware which evolved around the time
187.9 Implementing lazy functional languages on stock hardware: the.. - Jones (1992)(Correct)
The Spineless Tagless G-machine is an abstract machine designed to support nonstrict higher-order functional languages. This presentation of the machine falls into three parts. Firstly, we give a gene... / lazy functional languages on stock hardware the Spineless Tagless G-machine br of the STG language onto stock hardware. The success of an abstract
182.9 Real-Time Occlusion Culling for Models with Large Occluders - Coorg (1997)(Correct)
Efficiently identifying polygons that are visible from a
dynamic synthetic viewpoint is an important problem
in computer graphics. Typically, visibility determination
is performed using the z-buffer a... / of high performance z-buffer hardware a significant fraction of br machines have lesser or no hardware z- Address Technology
182.8 Home-based SVM protocols for SMP clusters: Design and Performance - Samanta (1998)(Correct)
As small-scale shared memory multiprocessors proliferate in the market, it is very attractive to construct largescale systems by connecting smaller multiprocessors together in software using efficient... / advantage of the intra-node hardware cache coherence and br task. In this environment the hardware coherence protocol operates at
178.7 MPI-FM: High Performance MPI on Workstation Clusters - Lauria, Chien (1997)(Correct)
Despite the emergence of high speed LANs, the communication performance available
to applications on workstation clusters still falls short of that available on MPPs.
A new generation of efficient mes... / is needed to take advantage of the hardware performance and to deliver it to br when used on new network hardware Our solution is to build
178.7 Small Forwarding Tables for Fast Routing Lookups - Degermark, Brodnik, Carlsson, Pink (1997)(Correct)
For some time, the networking community has assumed
that it is impossible to do IP routing lookups in software
fast enough to support gigabit speeds. IP routing
lookups must find the routing entry wit... / that has been thought to require hardware support at lookup frequencies of br at gigabit speeds without special hardware. The forwarding tables are very
177.2 Why Aren't Operating Systems Getting Faster As Fast as Hardware? - Ousterhout (1990)(Correct)
This paper evaluates several hardware platforms and operating systems using a set of benchmarks that stress kernel entry/exit, file systems, and other things related to operating systems. The overall ... / Getting Faster As Fast as Hardware John K. Ousterhout br This paper evaluates several hardware platforms and operating systems
175.3 Unifying Data and Control Transformations for Distributed Shared.. - Cierniak (1994)(Correct)
We present a unified approach to locality optimization that employs both data and control transformations. Data transformations include changing the array layout in memory. Control transformations inv... / Most shared-memory machines both hardware and software based rely on data br These protocols vary from hardware-only implementations to
174.4 Building Reliable Distributed Systems with CORBA - Landis, Maffeis (1997)(Correct)
New classes of large-scale distributed applications will
have to deal with unpredictable communication delays,
with partial failures, and with networks that
partition. In addition, sophisticated appli... / libraries or the underlying hardware can be exchanged as long as the br or on a certain operating system hardware or programming language and
173.5 Standard ML of New Jersey - Appel, MacQueen (1991)(Correct)
The Standard ML of New Jersey compiler has been under development for five years now. We have developed a robust and complete environment for Standard ML that supports the implementation of large soft... / runtime data format and hardware and some things were much br ML programs on a variety of hardware for which we do not yet have
173.1 A New Theory of Deadlock-Free Adaptive Routing in Wormhole Networks - Duato (1993)(Correct)
Second generation multicomputers use wormhole routing, allowing
a very low channel set-up time and drastically reducing the dependency
between network latency and internode distance. Deadlock-free
rou... / the implementation of fast hardware routers that reduce the br distinguished by message routing hardware that makes the topology of the
172.7 Continual Queries for Internet Scale Event-Driven Information Delivery - Liu (1999)(Correct)
In this paper we introduce the concept of continual queries, describe the design of a distributed event-driven continual query system \Gamma OpenCQ, and outline the initial implementation of OpenCQ on... / object model. An object can be a hardware or a software component e.g.a br from a diagnostic routine on a hardware component Furthermore the
171.0 Model Checking Large Software Specifications - Anderson (1996)(Correct)
In this paper we present our results and experiences of using symbolic model checking to study the specification of an aircraft collision avoidance system. Symbolic model checking has been highly succ... / highly successful when applied to hardware systems. We are interested in br successfully to a wide range of hardware systems. It has been surmised
165.2 The Relative Importance of Concurrent Writers and Weak Consistency.. - Keleher (1996)(Correct)
This paper presents a detailed comparison of the relative importance of allowing concurrent writers versus the choice of the underlying consistency model. Our comparison is based on single- and multip... / to overall performance. Hardware shared memory systems typically br than the cache lines used in hardware shared memory systems. DSM's
164.9 Practical Prefetching via Data Compression - Curewitz, Krishnan, Vitter (1993)(Correct)
An important issue that affects response time performance
in current OODB and hypertext systems is the I/O involved
in moving objects from slow memory to cache. A promising
way to tackle this problem ... / effect of cache misses MLG a hardware scheme of nonblocking and br needed ChB and a combined hardware and software approach which uses
162.8 Programmable Active Memories: a Performance Assessment - Bertin, Roncin, Vuillemin (1993)(Correct)
We present some quantitative performance measurements for the computing power of Programmable
Active Memories (PAM), as introduced by [BRV89]. Based on Field Programmable
Gate Array (FPGA) technology,... / technology the PAM is a universal hardware co-processor closely coupled to br computations through a specific hardware design. The performance
162.3 An Exploration of Nonprehensile Two-Palm Manipulation: Planning and.. - Erdmann (1995)(Correct)
This paper describes our current research into nonprehensile
palm manipulation. The term "palm" refers
to the use of the entire device surface during manipulation,
as opposed to use of the fingertips ... / . System Specifics For hardware we are using two Zebra Zero br have suffered from the frozen hardware problem. Too much of the
161.7 Verifying Systems with Replicated Components in Mur phi - Ip, Dill (1997)(Correct)
An extension to the Murphi verifier is presented to verify systems with replicated identical components. Although most systems are finite-state in nature, many of them are also designed to be scalable... / model checking Murphi hardware description language symmetry br Yang. Protocol verification as a hardware design aid. IEEE International
160.4 Energy Efficient Indexing On Air - Imielinski, Viswanathan, Badrinath (1994)(Correct)
We consider wireless broadcasting of data as a way of disseminating
information to a massive number of users. Organizing
and accessing information on wireless communication
channels is different from ... / efficient solutions both on hardware and software levels. This paper br There is a growing pressure on hardware vendors to come up with the
157.4 Model Checking for Security Protocols - Marrero, Clarke, Jha (1997)(Correct)
As more resources are added to computer networks, and as more vendors look to the World Wide Web as
a viable marketplace, the importance of being able to restrict access and to insure some kind of acc... / useful technique for verifying hardware designs. By modelling circuits br errors in real world designs. Like hardware designs security protocols are
154.6 Learning in the Presence of Malicious Errors - Kearns (1993)(Correct)
In this paper we study an extension of the distribution-free model of learning introduced by Valiant [23] (also known as the probably approximately correct or PAC model) that allows the presence of ma... / occur for example in the case of hardware errors. Thus we study a
154.5 MINERVA: A Second-Generation Museum Tour-Guide Robot - Thrun, Bennewitz, Burgard, Cremers.. (1999)(Correct)
This paper describes an interactive tour-guide robot, which
was successfully exhibited in a Smithsonian museum. During
its two weeks of operation, the robot interacted with
thousands of people, traver... / map learning path planning hardware interface modules motors br Greg Armstrong for his excellent hardware support. Special thanks also to
153.6 Microkernels Meet Recursive Virtual Machines - Ford (1996)(Correct)
This paper describes a novel approach to providingmodular and extensible operating system functionality and encapsulated environments based on a synthesis of microkernel and virtual machine concepts. ... / a microkernel running on generic hardware. A complete virtual machine br implemented on and export existing hardware architectures so they can
153.1 Modularity for Timed and Hybrid Systems - Alur, Henzinger (1997)(Correct)
In a trace-based world, the modular specification, verification, and control of live systems require each module to be receptive; that is, each module must be able to meet its liveness assumptions no ... / heterogeneous systems with mixed hardware and software components and
153.1 On the Importance of Checking Cryptographic Protocols for Faults - Boneh, DeMillo, Lipton (1997)(Correct)
We present a theoretical model for breaking various cryptographic schemes by taking advantage
of random hardware faults. We show how to attack certain implementations of RSA and Rabin
signatures. An i... / by taking advantage of random hardware faults. We show how to attack br also analyze the vulnerability to hardware faults of two identification
153.0 Multiresolution Modeling for Fast Rendering - Heckbert (1994)(Correct)
Three dimensional scenes are typically modeled using
a single, fixed resolution model of each geometric object.
Renderings of such a model are often either slow or
crude, however: slow for distant obj... / dollars. Advances in graphics hardware and memory technology have
150.6 Why Cryptosystems Fail - Anderson (1994)(Correct)
Designers of cryptographic systems are at a disadvantage to most other engineers, in that information on how their systems fail is hard to get: their major users have traditionally been government age... / heart an engineering problem. The hardware and software products which are br The first problem is thus that the hardware version of the product does not
148.9 Distributed Schedule Management in the Tiger Video Fileserver - Bolosky, Fitzgerald (1997)(Correct)
Tiger is a scalable, fault-tolerant video file server constructed from a collection of computers
connected by a switched network. All content files are striped across all of the computers and disks
in... / organization reduces the hardware cost per stream of video and br design of Tiger including the hardware organization data layout and
148.1 A Theoretical Evaluation of Selected Backtracking Algorithms - Kondrak (1994)(Correct)
In recent years, numerous new backtracking algorithms have been proposed. The algorithms are usually evaluated by empirical testing. This method, however, has its limitations. Our thesis adopts a diff... / measure because it depends on hardware and implementation and so
145.4 Parallel RAMs with Owned Global Memory and Deterministic Context-Free .. - Dymond, Ruzzo (1999)(Correct)
We identify and study a natural and frequently occurring subclass
of Concurrent Read, Exclusive Write Parallel Random Access
Machines (CREW-PRAMs). Called Concurrent Read, Owner Write,
or CROW-PRAMs, ... / model implemented using physical hardware in which every memory cell is br between the amounts of hardware used on the two machines.Our
144.9 Mariposa: a wide-area distributed database system - Stonebraker, Aoki, Litwin, Pfeffer.. (1996)(Correct)
The requirements of wide-area distributed database systems differ dramatically from those of local-area network systems. In a wide-area network (WAN) configuration, individual sites usually report t... / California with a wide variety of hardware and storage capacities. Each br unique features of a particular hardware architecture. As a result
144.6 High-Performance Local Area Communication With Fast Sockets - Rodrigues, Anderson, Culler (1997)(Correct)
Modern switched networks such as ATM and Myrinet
enable low-latency, high-bandwidth communication.
This performance has not been realized by current
applications, because of the high processing overhe... / to the ability of modern network hardware however. While TCP is capable br are similar to the underlying hardware. All of these systems realize
144.6 Software DSM Protocols that Adapt between Single Writer and Multiple.. - Cristiana Amza (1997)(Correct)
We present two software DSM protocols that dynamically
adapt between a single writer (SW) and a
multiple writer (MW) protocol based on the application
's sharing patterns. The first protocol (WFS)
ad... / memory DSM on commodity hardware. Both single writer SW and br and Brorsson describe hardware cache-coherence protocols that
144.6 A High-performance Endsystem Architecture for Real-time CORBA - Douglas Schmidt (1997)(Correct)
Many application domains (such as avionics, telecommunications,
and multimedia) require real-time guarantees from
the underlying networks, operating systems, and middleware
components to achieve their... / ATM and Fast Ethernet ffl Hardware such as RISC vs. CISC. The br management On modern RISC hardware data copying consumes a
139.1 CPU Inheritance Scheduling - Bryan Ford (1996)(Correct)
Traditional processor scheduling mechanisms in operating
systems are fairly rigid, often supportingonly one fixed
scheduling policy, or, at most, a few "scheduling classes"
whose implementations are c... / has waxed and waned following hardware and application trends. In the br in many existing kernels that hardware interrupt handlers consume little
139.1 The Galley Parallel File System - Nieuwejaar (1996)(Correct)
Most current multiprocessor file systems are designed to use multiple disks in parallel, using the high
aggregate bandwidth to meet the growing I/O requirements of parallel scientific applications. Ma... / has not been keeping pace. Hardware limitations are one reason for
137.1 Stack-Based Typed Assembly Language - Morrisett, Crary, Walker, Glew (1998)(Correct)
In previous work, we presented Typed Assembly Language (TAL). TAL is sufficiently expressive to serve as a target language for compilers of high-level languages such as ML. That work assumed such a co... / many machine architectures have hardware mechanisms that expect programs
137.0 The UNIX Time-Sharing System - Ritchie, Thompson (1974)(Correct)
Unix is a general-purpose, multi-user, interactive operating system for the larger Digital Equipment Corporation PDP-11 and the Interdata 8/32 computers. It offers a number of features seldom found ev... / or in human effort it can run on hardware costing as little as br Text Formatting Programs. Ii. Hardware And Software Environment The
136.3 Drawing the Red Line in Java - Back, Hsieh (1999)(Correct)
Software-based protection has become a viable alternative
to hardware-based protection in systems based on languages
such as Java, but the absence of hardware mechanisms
for protection has been couple... / become a viable alternative to hardware-based protection in systems based br such as Java but the absence of hardware mechanisms for protection has
131.9 Application Scheduling and Processor Allocation in Multiprogrammed.. - Sevcik (1993)(Correct)
When large-scale multiprocessors for parallel processing are subjected to heavy diverse workloads of applications,
it will be necessary to schedule them in a multiprogrammed fashion in order to use th... / can be provided in hardware since all memory requests use the br of processors in the system the hardware bound When A p speedup
131.9 A Sanctuary for Mobile Agents - Yee (1997)(Correct)
ly, this is a circuit of the (complete) graph connecting the airline servers, and the originator may chose this circuit at the time of agent dispatch. At any honest server, the agent code and its read... / are likely to consist of identical hardware running copies of the same br permit agents to exist both in a hardware-based secure environment and in
130.4 Network Objects - Birrell, Nelson, Owicki, Wobber (1995)(Correct)
A network object is an object whose methods can be invoked over a network. The Modula-3
network objects system is novel for its overall simplicity. It provides distributed type safety
through the narr... / value of our ideas by building hardware and software prototypes and
130.4 An Argument for Simple COMA - Ashley Saulsbury (1995)(Correct)
We present design details and some initial performance
results of a novel scalable shared memory
multiprocessor architecture. This architecture features
the automatic data migration and replication ca... / without the accompanying hardware complexity. A software layer br DVSM systems leaving simpler hardware to maintain shared memory
130.4 Two examples of verification of multirate timed automata with Kronos - Daws, Yovine (1995)(Correct)
Multirate timed automata [2] are an extension of timed
automata [3] where each clock has its own speed varying
between a lower and an upper bound that may change
from one control location to another. ... / a real-time protocol running on hardware with clocks that measure time br end with two -bits. Besides the hardware clocks drift with some known
130.0 An Evaluation of Directory Schemes for Cache Coherence - Agarwal, al. (1988)(Correct)
The problem of cache coherence in shared-memory multiprocessors has been addressed using two basic approaches: directory schemes and snoopy cache schemes. Directory schemes have been given less attent... / cache coherency support in hardware. These snoopy cache schemes also br must be carried out for every hardware model desired. A problem with
129.8 A Review of Evolutionary Artificial Neural Networks - Yao (1993)(Correct)
Research on potential interactions between connectionist learning systems, i.e., artificial neural networks (ANNs), and evolutionary search procedures, like genetic algorithms (GAs), has attracted a l... / weights and architectures as its hardware it is easier to understand the
127.8 Throughput-Competitive On-Line Routing - Awerbuch (1993)(Correct)
We develop a framework that allows us to address the issues of admission control and
routing in high-speed networks under the restriction that once a call is admitted and routed,
it has to proceed to ... / networks and stems from current hardware limitations in particular the
124.6 Trustee-based Tracing Extensions to Anonymous Cash and the Making of.. - Brickell, Gemmell, Kravitz (1995)(Correct)
Electronic cash is a subject of great economic, political,
and research importance. With advances in computer
networks, in processor speed, and in databases and with
advances in note counterfeiting te... / requires no tamper-resistant hardware and can be implemented as either br and tamper-detecting hardware automatically alerts the user in
123.4 Number-Theoretic Constructions of Efficient Pseudo-Random Functions - Naor, Reingold (1997)(Correct)
We describe efficient constructions for various cryptographic primitives (both in privatekey
and in public-key cryptography). We show these constructions to be at least as secure as
the decisional ver... / the functions in parallel and in hardware implementations. . Has br functions will be implemented in hardware as is the case for DES In
123.4 Bucket Hashing and its Application to Fast Message Authentication - Rogaway (1997)(Correct)
We introduce a new technique for constructing a family of universal hash functions.
At its center is a simple metaphor: to hash a string x, cast each of its words into a small
number of buckets; xor... / will usually be no special-purpose hardware to help out MAC generation and br Though originally intended for hardware these techniques are fast in
121.7 Performance Analysis Using the MIPS R10000 Performance Counters - Zagha, Larson, Turner, Itzkowitz (1996)(Correct)
Tuning supercomputer application performance often requires analyzing the interaction of the
application and the underlying architecture. In this paper, we describe support in the MIPS R10000
for n... / of multi-level memory hierarchies hardware-based cache coherence and br using an integrated set of hardware mechanisms operating system
118.8 MGS: A Multigrain Shared Memory System - Yeung (1996)(Correct)
Parallel workstations, each comprising 10-100 processors, promise cost-effective general-purpose multiprocessing. This paper explores the coupling of such small- to medium-scale shared memory multipro... / enables the collaboration of hardware and software shared memory and br VLSI networks and special-purpose hardware support for shared memory. These
118.8 iKP - A Family of Secure Electronic Payment Protocols - Bellare, Garay, Hauser, Herzberg.. (1995)(Correct)
Mihir Bellare
y
, Juan A. Garay
z
, Ralf Hauser
x
, Amir Herzberg
z
,
Hugo Krawczyk
z
, Michael Steiner
x
, Gene Tsudik
x
, Michael Waidner
x
August 2, 1995
Abstract
This paper propose... / implemented in either software or hardware. Individual protocols differ in br implemented either in software or hardware. In fact in KP and KP the
117.2 Reducing Memory Latency via Non-blocking and Prefetching Caches - Chen (1992)(Correct)
Non-blocking caches and prefetching caches are two techniques for hiding memory latency by exploiting the overlap of processor computations with data accesses. A non-blocking cache allows execution to... / the effectiveness of these two hardware-based schemes. We propose a br the SPEC benchmarks show that the hardware prefetching caches generally
115.9 A Survey of QoS Architectures - Aurrecoechea, Campbell, Hauw (1996)(Correct)
Over the past several years there has been a considerable amount of research within the field of quality of service (QoS) support for distributed multimedia systems. To date, most of the work has been... / protocols and the use of hardware assists for efficient protocol
115.4 Evaluation of Release Consistent Software Distributed Shared Memory.. - Sandhya Dwarkadas (1993)(Correct)
We evaluate the effect of processor speed, network characteristics,
and software overhead on the performance
of release-consistent software distributed shared memory.
We examine five different protoco... / implementation in a particular hardware and software environment br software. Furthermore the hardware environments of many of these
114.8 BSPlib - The BSP Programming Library - Hill, McColl, Stefanescu, Goudreau.. (1997)(Correct)
This memory area is regarded as unregistered. 6. While registration is designed for "full duplex" communication, a process can do half duplex communication by, appropriately, registering an area of si... / provide a clear focus for future hardware developments. For a model to br the performance of software and hardware must be scalable from a single
113.5 Turning SOS Rules into Equations - Aceto, Bloom, Vaandrager (1994)(Correct)
Many process algebras are defined by structural operational semantics (SOS). Indeed,
most such definitions are nicely structured and fit the GSOS format of [19]. We
give a procedure for converting any... / compilation techniques hardware implementations and logics br Amsterdam . G. Berry. A hardware implementation of Pure Esterel.
113.4 Adaptive Cache Coherency for Detecting Migratory Shared Data - Cox, Fowler (1993)(Correct)
Parallel programs exhibit a small number of distinct datasharing
patterns. A common data-sharing pattern, migratory
access, is characterized by exclusive read and write access
by one processor at a t... / would not significantly increase hardware cost. We use trace- and br are simple enough to build into hardware cache controllers without a large
113.0 Validity Checking for Combinations of Theories with Equality - Barrett, Dill, Levitt (1996)(Correct)
An essential component in many verification methods is a fast decision procedure for validating logical expressions. This paper presents the algorithm used in the Stanford Validity Checker (SVC) whi... / been used to aid several realistic hardware verification efforts. The logic br verifying the correctness of hardware designs in particular are
111.1 Thwarting the Power-Hungry Disk - Douglis, Krishnan, Marsh (1994)(Correct)
Minimizing power consumption is important for mobile computers, and disks consume a significant portion of system-wide power. There is a large difference in power consumption between a disk that is sp... / power consumption through both hardware and software approaches. One area br The Powerbook trace on the same hardware shows a improvement in energy
110.1 Embra: Fast and Flexible Machine Simulation - Witchel, Rosenblum (1996)(Correct)
This paper describes Embra, a simulator for the processors, caches, and memory systems of uniprocessors and cache-coherent multiprocessors. When running as part of the SimOS simulation environment, Em... / multiprocessors. Embra models the hardware of these machines in enough br modeling of memory management hardware for instruction fetches and data
109.0 Exploiting Positive Equality in a Logic of Equality with.. - Bryant, German, Velev (1999)(Correct)
In using the logic of equality with unininterpreted functions to verify
hardware systems, specific characteristics of the formula describing the correctness
condition can be exploited when deciding ... / functions to verify hardware systems specific characteristics br suitable abstractions to the hardware model we can express the
108.6 A High-Performance Microarchitecture with Hardware-Programmable.. - Razdan, Smith (1994)(Correct)
This paper explores a novel way to incorporate hardware-programmable
resources into a processor microarchitecture to improve the
performance of general-purpose applications. Through a coupling
of comp... / Microarchitecture with Hardware-Programmable Functional Units br a novel way to incorporate hardware-programmable resources into a
108.5 Watermarking Techniques for Intellectual Property Protection - Kahng, Lach, Mangione-Smith, Mantik, .. (1998)(Correct)
Digital system designs are the product of valuable effort and knowhow.
Their embodiments, from software and HDL program down
to device-level netlist and mask data, represent carefully guarded
intellec... / design methodologies for both hardware and software have been embraced br apply to the protection of both hardware and software e.g.Verilog or
107.2 The Tiger Video Fileserver - Bolosky, Barrera, III, Draves.. (1996)(Correct)
Tiger is a distributed, fault-tolerant real-time fileserver. It
provides data streams at a constant, guaranteed rate to a
large number of clients, in addition to supporting more
traditional filesystem... / the load. Figure Basic Tiger Hardware Layout In addition to the cubs br and hence will not compete for hardware resources with the other
107.2 Techniques for Reducing Consistency-Related Communication in.. - Carter, Bennett, Zwaenepoel (1993)(Correct)
Distributed shared memory (DSM) is an abstraction of shared memory on a distributed memory machine. Hardware DSM systems support this abstraction at the architecture level; software DSM systems suppor... / on a distributed memory machine. Hardware DSM systems support this br not require complex and expensive hardware cache controllers The
106.3 Disco: Running Commodity Operating Systems on Scalable Multiprocessors - Bugnion, al. (1997)(Correct)
this paper we examine the problem of extending modern operating
systems to run efficiently on large-scale shared memory multiprocessors
without a large implementation effort. Our approach
brings back ... / these machines has often trailed hardware in reaching the functionality and br layer of software between the hardware and operating system. This layer
106.3 IP Switching and Gigabit Routers - Newman, Minshall, Lyon, Huston (1997)(Correct)
This paper examines two approaches to
the design of a high-performance router, the gigabit router and the IP switch, and then provides some
detail on the implementation of an IP switch and the protoco... / of an ATM switch is that the hardware is standardized and is available br advanced features such as hardware Quality of Service QoS support
106.3 Accelerated Occlusion Culling using Shadow Frusta - Hudson, Manocha, Cohen, Lin, Hoff.. (1997)(Correct)
Many applications in computer graphics and virtual environments
need to render datasets with large numbers of primitives
and high depth complexity at interactive rates. However, standard
techniques... / like view frustum culling and a hardware z-buffer are unable to display br of polygons. Current graphics hardware provides support for visibility
103.7 Software-Extended Coherent Shared Memory: Performance and Cost - Chaiken, Agarwal (1994)(Correct)
This paper evaluates the tradeoffs involved in the design of the
software-extended memory system of Alewife, a multiprocessor architecture
that implements coherentsharedmemory through a combination
of... / through a combination of hardware and software mechanisms. For each br coherence directory pointers in hardwareand allows software to handle
103.7 Distributed Filaments: Efficient Fine-Grain Parallelism on a Cluster.. - Freeh, Lowenthal, Andrews (1994)(Correct)
A fine-grain parallel program is one in which processes are typically small, ranging from
a few to a few hundred instructions. Fine-grain parallelism arises naturally in many
situations, such as itera... / runs on existing off-the-shelf hardware and software. It has a simple br paradigm. DF requires no special hardware support for a shared-memory
102.8 The Effect of Instruction Fetch Bandwidth on Value Prediction - Gabbay, Mendelson (1998)(Correct)
Value prediction attempts to eliminate true-data
dependencies by dynamically predicting the outcome
values of instructions and executing true-data dependent
instructions based on that prediction. In t... / of value prediction and its hardware organization. . Introduction br execution model where the hardware is expected to extract the
102.8 Integrating Path and Timing Analysis using Instruction-Level.. - Lundqvist, Stenström (1998)(Correct)
Previously published methods for estimation of the worstcase
execution time on contemporary processors with complex pipelines
and multi-level memory hierarchies result in overestimations owing to in... / detailed timing analysis of hardware platforms. Second by extending br on the actual WCET for a given hardware platform. There are two
102.1 Java Access to Numerical Libraries - Casanova (1997)(Correct)
It is a common and somewhat erroneous belief that Java will always be "too slow" for scientific
computing. Two projects underway at the University of Tennessee are addressing the question of scientifi... / computational resources such as hardware and software distributed across br Java source code is compiled into hardware independent bytecode which is
102.0 Adaptive Execution in Complex Dynamic Worlds - Firby (1989)(Correct)
Adaptive Execution in Complex Dynamic Worlds
Robert James Firby
Yale University
1989
A robot acting in the real world must use flexible plans because actions will sometimes
fail to produce desired ef... / the RAP Memory . . The Hardware Interface and The RAP Interpreter br . The Memory Model . The Hardware Interface . The Primitive
101.4 The Synergy Between Non-blocking Synchronization and Operating System .. - Greenwald, Cheriton (1996)(Correct)
Non-blocking synchronization has significant advantages over
blocking synchronization: however, it has not been used to a
significant degree in practice. We designed and implemented
a multiprocessor o... / for our approach and a potential hardware implementation. Section br instruction tries to read U the hardware interlocks as it already does
101.2 Metasystems: An Approach Combining Parallel Processing and.. - Grimshaw (1994)(Correct)
A metasystem is a single computing resource composed of a heterogeneous group of autonomous computers
linked together by a network. The interconnection network needed to construct large metasystems
wi... / and coercion and schedules all hardware resources across the different br broad categories of heterogeneity hardware and software. Hardware
98.5 Falcon: On-line Monitoring and Steering of Large-Scale Parallel.. - Gu (1995)(Correct)
Falcon is a system for on-line monitoring and steering of large-scale parallel programs. The purpose of such interactive steering is to improve its performance or to affect its execution behavior. The... / basis. Falcon runs on several hardware platforms including the Kendall br library available on several hardware platforms including the Kendall
98.5 The Design and Implementation of Arjuna - Parrington, al. (1995)(Correct)
Record // Important utility class
RecoveryRecord // handles object recovery
LockRecord // handles object locking
RecordList // Intentions list
other management record types
To make use of atomic acti... / install and run on a variety of hardware and software configurations. In br It will be assumed that the hardware components of the system are
97.8 A Layered Architecture for Office Delivery Robots - Simmons, Goodwin, Haigh, Koenig.. (1997)(Correct)
Office delivery robots have to perform many tasks.
They have to determine the order in which to visit offices,
plan paths to those offices, follow paths reliably,
and avoid static and dynamic obstacle... / with the commercially available hardware robot base and pan-tilt head br Navigation Obstacle Avoidance Hardware Figure Flow of Information
97.8 Constructing Reliable Distributed Communication Systems with CORBA - Maffeis (1997)(Correct)
Communication software and distributed services for nextgeneration applications must be reliable, efficient, flexible, and reusable. These requirements motivate the use of the Common Object Request Br... / communication protocols and hardware. For instance two CORBA objects br languages operating systems or hardware platforms. CORBA's synchronous
97.1 A General Framework for Mesh Decimation - Kobbelt, Campagna, Seidel (1998)(Correct)
The decimation of highly detailed meshes has emerged
as an important issue in many computer graphics related
fields. A whole library of different algorithms has
been proposed in the literature. By car... / through-put of today's graphics hardware. Hence in order to be able to
95.6 Classification And Detection Of Computer Intrusions - Kumar (1995)(Correct)
Some computer security breaches cannot be prevented using access and information flow control techniques. These breaches may be a consequence of system software bugs, hardware or software failures, in... / to the department by keeping the hardware and software well tuned well br of system software bugs hardware or software failures incorrect
95.6 Message-Passing Performance of Various Computers - Dongarra, Dunigan (1995)(Correct)
This report compares the performance of different computer systems for basic message-passing. Latency and bandwidth are measured on Convex, Cray, IBM, Intel, KSR, Meiko, nCUBE, NEC, SGI, and TMC multi... / processors are interconnected by hardware and software to attack various br fundamental parameters on a given hardware platform to help in building
95.6 Fast Multiresolution Surface Meshing - Gross, Gatti, Staadt (1995)(Correct)
We are presenting a new method for adaptive surface meshing and triangulation which controls the local level--of--detail of the surface approximation by local spectral estimates. These estimates are f... / since most modern graphics hardware support the display of shaded and
94.8 Memory Consistency Models - Mosberger (1993)(Correct)
This paper discusses memory consistency models and their influence on software in the context of parallel machines. In the first part we review previous work on memory consistency models. The second p... / model to a much higher degree than hardware GGH by enabling br memory can be implemented at the hardware or software level. In the latter
93.8 Public International Benchmarks for Parallel Computers - Hockney, Berry (1994)(Correct)
this report: David Bailey (NASA Ames Research Center)
, Michael Berry (University of Tennessee), Jack Dongarra (University of Tennessee/Oak
Ridge National Laboratory), Vladimir Getov (University of So... / . . Hardware Performance br since these either involve basic hardware and software tests such as
92.7 NetCash: A design for practical electronic currency on the Internet - Medvinsky (1993)(Correct)
NetCash is a framework that supports realtime electronic payments
with provision of anonymity over an unsecure network.
It is designed to enable new types of services on the Internet
which have not be... / operation transferability and hardware independence. Some of these br that assures security. Hardware independence To prevent double
92.7 Silicon Evolution - Thompson (1996)(Correct)
The advent of new families of reconfigurable
integrated circuits makes it possible
for artificial evolution to manipulate
a real physical substrate to produce electronic
circuits evaluated in the real... / appropriate. The reconfigurable hardware is a continuous-time analogue br detail on what reconfigurable hardware is how it can be evolved and
92.7 A Survey of Distributed Garbage Collection Techniques - Plainfossé, Shapiro (1995)(Correct)
This paper is organised as follows. Section 2 first introduces our object
model. Section 3 describes the reference count-based approach. In particular,
we compare those techniques according to their r... / may fail due to software or hardware problems. We only consider
91.4 Combining Symbolic Model Checking with Uninterpreted Functions for.. - Sergey Berezin (1998)(Correct)
We present a new approach to the verification of hardware systems with data dependencies using
temporal logic symbolic model checking. As a benchmark we take Tomasulo's algorithm [HP96]
for out-of-ord... / approach to the verification of hardware systems with data dependencies br are written back. In the actual hardware implementations of Tomasulo's
89.8 Markovian Analysis of Large Finite State Machines - Hachtel, Macii, Pardo, Somenzi (1996)(Correct)
Regarding finite state machines as Markov chains facilitates the application of probabilistic methods
to very large logic synthesis and formal verification problems. In this paper we present symbolic
... / become of interest. Beside formal hardware verification other successful br state machines modeling real hardware modules may be used to perform
89.8 Software Transactional Memory - Shavit (1995)(Correct)
As we learn from the literature, flexibility in choosing synchronization
operations greatly simplifies the task of designing
highly concurrent programs. Unfortunately, existing
hardware is inflexible ... / programs. Unfortunately existing hardware is inflexible and is at best on br on a single word. Building on the hardware based transactional
89.8 Reliable Broadband Communication Using a Burst Erasure Correcting Code - McAuley (1990)(Correct)
Traditionally, a transport protocol corrects errors in a
computer communication network using a simple ARQ
protocol. With the arrival of broadband networks, forward
error correction is desirable as a ... / and . The design of the FEC hardware is computationally demanding br in the link. Though FEC requires hardware to run at even moderate
88.8 The Performance Impact of Flexibility in the Stanford FLASH.. - Heinrich (1994)(Correct)
Several multiprocessors have been proposed that offer programmable implementations of scalable cache coherence as well as support for message passing. In the FLASH machine, flexibility is obtained by ... / MAGIC and from protocol-specific hardware optimizations. In this paper we br MAGIC's macropipeline with a full hardware implementation and assume that
88.2 Limitations of the Kerberos Authentication System+ - Bellovin (1991)(Correct)
The Kerberos authentication system, a part of MIT's Project Athena, has been
adopted by other organizations. Despite Kerberos's many strengths, it has a number of
limitations and some weaknesses. Some... / how specialpurpose cryptographic hardware may be needed in some cases. br without employing special-purpose hardware no matter what the design of
85.7 Eliminating Conflict Misses for High Performance Architectures - Rivera, Tseng (1998)(Correct)
Many cache misses in scientific programs are due to conflicts
caused by limited set associativity. Two data-layout transformations,
inter- and intra-variable padding, can eliminate
many conflict misse... / on modern microprocessors. Due to hardware constraints caches have limited br Conflicts may be eliminated with hardware or operating systems
85.7 Cooperative Multiagent Robotic Systems - Arkin, Balch (1998)(Correct)
Introduction
Teams of robotic systems at first glance might appear to be more trouble than they are worth. Why
not simply build one robot that is capable of doing everything we need? There are severa... / .she demonstrated in hardware group behaviors such as flocking
85.1 The Influence of Caches on the Performance of Heaps - LaMarca, Ladner (1997)(Correct)
As memory access times grow larger relative to processor cycle times, the cache performance of algorithms
has an increasingly large impact on overall performance. Unfortunately, most commonly used
alg... / analysis is currently done with hardware monitoring or with
85.1 The Saphira Architecture: A Design for Autonomy - Konolige, Myers, Ruspini, Saffiotti (1997)(Correct)
Journal of Experimental and Theoretical Artificial Intelligence (JETAI) 9, 1997, 215-235.
Special issue on Architectures for Physical Agents.
Mobile robots, if they areto perform useful tasks andbecom... / completed in one day so the robot hardware and software had to be very br isolate the specifics of the robot hardware from the agent architecture
85.1 Timed Asynchronous System Model - Cristian, Fetzer (1997)(Correct)
We propose a formal definition for the timed asynchronous
system model, we describe extensive measurements
of actual message and process scheduling
delays and hardware clock drifts that confirm
that t... / and process scheduling delays and hardware clock drifts that confirm that br processes have no access to hardware clocks. Because in the time-free
85.1 An Efficient Implementation of Reactivity for Modeling Hardware in.. - Liao, Tjiang, Gupta (1997)(Correct)
Reactivity is one of the key features of hardware
description languages. We present an efficient implementation
of reactivity in the Scenic framework that allows the system
designer to model hardware ... / of Reactivity for Modeling Hardware in the Scenic Design Environment br is one of the key features of hardware description languages. We
84.0 Lazy Receiver Processing (LRP): A Network Subsystem Architecture for.. - Druschel (1996)(Correct)
The explosive growth of the Internet, the widespread use
of WWW-related applications, and the increased reliance
on client-server architectures places interesting new demands
on network servers. In pa... / network load. The architecture is hardware independent and does not degrade br have lower priority than hardware interrupts thus the reception
84.0 Scenario-Based Analysis of Software Architecture - Kazman (1996)(Correct)
Software architecture is one of the most important tools for designing and understanding
a system, whether that system is in preliminary design, active deployment, or
maintenance. Scenarios are impo... / performed by either software or hardware components. We also say a br may also depend upon code-level or hardware-level factors such as byte
83.9 Separating Data and Control Transfer in Distributed Operating Systems - Thekkath, Levy, Lazowska (1994)(Correct)
Advances in processor architecture and technology have resulted in workstations in the 100+ MIPS
range. As well, newer local-area networks such as ATM promise a ten- to hundred-fold increase in
throug... / of distributed systems at the hardware level and that distributed br our model on DECstation hardware connected by an ATM network. We
82.4 Scientific Computing on Bulk Synchronous Parallel Architectures - Bisseling, McColl (1993)(Correct)
Bulk synchronous parallel architectures offer the prospect of achieving both scalable
parallel performance and architecture independent parallel software. They provide
a robust model on which to base ... / parameters that characterise the hardware g is the communication br data partitioning instead of on hardware dependent techniques that take
81.8 Efficient Support for P-HTTP in Cluster-Based Web Servers - Aron, Druschel, Zwaenepoel (1999)(Correct)
This paper studies mechanisms and policies
for supporting HTTP/1.1 persistent connections
in cluster-based Web servers that employ contentbased
request distribution. We present two mechanisms
for the ... / becoming an increasingly popular hardware platform for cost-effective high br uses substantially more powerful hardware than the back-ends. It is
81.4 Supercomputer Performance Evaluation and the Perfect Benchmarks - Cybenko (1990)(Correct)
In the past three years, the Perfect Benchmark
TM
Suite has evolved
from a supercomputer performance evaluation plan, presented by Kuck
and Sameh at the 1987 International Conference on Supercomputi... / in large part to increases in hardware speed averaging an order of br In recent years the progress of hardware technology has begun to slow as
80.8 Differential Fault Analysis of Secret Key Cryptosystems - Biham, Shamir (1997)(Correct)
In September 1996 Boneh, Demillo, and Lipton from Bellcore announced a new type of cryptanalytic attack which exploits computational errors to find cryptographic keys. Their attack is based on algebra... / demonstrated that under the same hardware fault model used by the Bellcore br fault model based on permanent hardware faults and show that it can be
80.8 Trace-Based Mobile Network Emulation - Noble, Satyanarayanan, Nguyen, Katz (1997)(Correct)
Subjecting a mobile computing system to wireless network
conditions that are realistic yet reproducible is a challenging
problem. In this paper, we describe a technique called trace
modulation that re... / out without mobile network hardware or physical motion. It is br drift on our trace collection hardware can be significant relative to
80.8 Applying Compiler Techniques to Cache Behavior Prediction - Ferdinand, Martin, Wilhelm (1997)(Correct)
In previous work [1], we have developed the theoretical
basis for the prediction of the cache behavior of programs
by abstract interpretation. Abstract interpretation
is a technique for the static ana... / tailored for the analysis of hardware with states is presented. This br estimations. For example for hardware with caches the typical worst
79.9 Improving Wireless LAN Performance via Adaptive Local Error Control - Eckhardt, Steenkiste (1998)(Correct)
Wireless links can exhibit high error rates due to attenuation,
fading, or interfering active radiation sources. To
make matters worse, error rates can be highly variable due
to changes in the wireles... / The lowest level solution is hardware error control techniques such as br with a transparent low-level hardware approach. An alternative is
79.9 Locating Objects in Wide-Area Systems - van Steen, Hauck, Homburg, Tanenbaum (1998)(Correct)
Locating mobile objects in a worldwide system requires a scalable location service. An object can be a telephone or a notebook computer, but also a software or data object, such as a file or an electr... / may be implemented in software hardware or a combination thereof are br systems we assume that all hardware and software objects have
79.4 On Non-Preemptive Scheduling of Periodic and Sporadic Tasks - Jeffay, Stanat, Martel (1991)(Correct)
This paper examines a fundamental problem in
the theory of real-time scheduling, that of scheduling a set
of periodic or sporadic tasks on a uniprocessor without
preemption and without inserted idle... / monitors embedded in it and hardware for tracking the position of the br scheduling properties of device hardware and software either make
78.2 A Quantitative Analysis of Loop Nest Locality - McKinley, Temam (1996)(Correct)
This paper analyzes and quantifies the locality characteristics of numerical loop nests in order to suggest future directions for architecture and software cache optimizations. Since most programs spe... / Smith's bibliographies on hardware aspects of cache memories Smi br nests. For example software and hardware prefetching exploit the spatial
78.2 Optimizing Instruction Cache Performance for Operating System.. - Torrellas, Xia, Daigle (1995)(Correct)
High instruction cache hit rates are key to high performance. One known technique to
improve the hit rate of caches is to use an optimizing compiler to minimize cache interference
via an improved layo... / Firstly with the help of a hardware performance monitor we br Setup This section examines the hardware and software systems used to
76.6 A Polygonal Approximation to Direct Scalar Volume Rendering - Shirley, Tuchman (1990)(Correct)
One method of directly rendering a three-dimensional volume
of scalar data is to project each cell in a volume onto
the screen. Rasterizing a volume cell is more complex than
rasterizing a polygon. A ... / tetrahedral volume cells with hardware renderable transparent br primatives. Kaufman describes a hardware design that scan converts volume
76.5 Quantitative Analysis and Model Checking - Huth (1997)(Correct)
Many notions of models in computer science provide quantitative information, or uncertainties, which necessitate a quantitative model checking paradigm. We present such a framework for reactive and ge... / verification especially in hardware design. Model checking as such
76.5 Interprocedural Conditional Branch Elimination - Bodik (1997)(Correct)
The existence of statically detectable correlation among conditional branches enables their elimination, an optimization that has a number of benefits. This paper presents techniques to determine whet... / speculative execution and hardware branch prediction and ffl br Research in correlationbased hardware branch prediction shows that
76.5 An Architecture for Optimal All-to-All Personalized Communication - Hinrichs, Kosak, O'Hallaron.. (1994)(Correct)
In all-to-all personalized communication (AAPC), every node of a parallel system sends a potentially
unique packet to every other node. AAPC is an important primitive operation for modern parallel
com... / utilizing all links. A simple hardware addition for synchronized br for the evaluation of the hardware complexity as well as possible
76.5 Discretized Marching Cubes - Montani, Scateni, Scopigno (1994)(Correct)
Since the introduction of standard techniques for isosurface extraction from volumetric datasets, one of the hardest problems has been to reduce the number of triangles (or polygons) generated. This p... / per surface. State-of-the-art hardware is not yet fast enough to
76.2 Fail-safe PVM: A portable package for distributed programming with.. - Leon (1993)(Correct)
Many scientific problems benefit from computationsthat are parallel at a coarse grain. Collections of looselycoupled, heterogeneous computers are increasingly being applied to these problems. While in... / some supercomputers special hardware workstations networks of br abstracted view of the underlaying hardware. Availability is achieved by
75.3 A Parallel Workload Model and Its Implications for Processor.. - Allen Downey (1996)(Correct)
We develop a workload model based on the observed behavior of parallel
computers at the San Diego Supercomputer Center and the Cornell
Theory Center. This model gives us insight into the performance o... / speedup-bound at first by the hardware limit linear speedup and then
75.3 Formulations and Formalisms in Software Architecture - Shaw (1995)(Correct)
Software architecture is the level of software design that addresses the overall structure and properties of software systems. It provides a focus for certain aspects of design and development that ... / precision and accuracy minimum hardware configuration security need to br need to access specialized hardware For example this product
74.2 Enabling Large-scale Simulations: Selective Abstraction Approach to.. - Huang, Estrin, Heidemann (1998)(Correct)
ion Approach to The Study of Multicast Protocols
Polly Huang, Deborah Estrin, John Heidemann
USC/Information Science Institute
University of Southern California
4676 Admiralty Way, Suite 1001
Marina d... / but it can require expensive hardware and have high overhead. In this br simulation can also require hardware which is not widely available or