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This directory is created automatically and some papers may be mislabeled. Only document within the CiteSeer database are listed. The directory is intended to provide entry points for browsing the database and is not intended to be authoritative. Papers may not appear in all relevant categories. For example, papers in a sub-category may not appear in higher level categories.

1208   Graph-Based Algorithms for Boolean Function Manipulation - Bryant (1986)   (Correct)
163   Formal Methods: State of the Art and Future Directions - Clarke, Wing (1996)   (Correct)
92   Experience With a Learning Personal Assistant - Mitchell, Caruana, Freitag.. (1994)   (Correct)
79   Programmable Active Memories: a Performance Assessment - Bertin, Roncin, Vuillemin (1993)   (Correct)
52   Assigning Confidence to Conditional Branch Predictions - Jacobsen, Rotenberg, Smith (1996)   (Correct)
51   Asynchronous Design Methodologies: An Overview - Hauck (1995)   (Correct)
45   Symbolic Model Checking with Partitioned Transition Relations - Burch, Clarke, Long (1991)   (Correct)
43   Algorithms for synthesis of hazard-free asynchronous circuits - Lavagno, Keutzer.. (1991)   (Correct)
43   Virtual Wires: Overcoming Pin Limitations in FPGA-based Logic.. - Jonathan Babb (1993)   (Correct)
43   Virtual Wires' Overcoming Pin Limitations in FPGA-based Logic.. - Babb, Tessier, Agarwal (1993)   (Correct)
40   Microprocessor Design Verification - Warren Hunt (1989)   (Correct)
31   A Micropipelined ARM - Furber, Day, Garside, Paver, Woods (1993)   (Correct)
29   OneChip: An FPGA Processor With Reconfigurable Logic - Wittig (1995)   (Correct)
27   New Performance-Driven FPGA Routing Algorithms - Alexander, Robins (1996)   (Correct)
26   The Complexity of the Optimal Variable Ordering Problems of A Shared.. - Tani, Hamaguchi, Yajima (1993)   (Correct)
25   Silicon Auditory Processors as Computer Peripherals - Lazzaro (1993)   (Correct)
19   Symmetry Detection and Dynamic Variable Ordering of Decision Diagrams - Panda, Somenzi, Plessier (1996)   (Correct)
18   Guarded Evaluation: Pushing Power Management to Logic Synthesis/Design - Tiwari, Malik, Ashar (1995)   (Correct)
18   Guarded Evaluation : Pushing Power Management to Logic.. - Tiwari, Malik, Ashar (1996)   (Correct)
17   The SNAP Project: Design of Floating Point Arithmetic Units - Oberman, Al-Twaijry, Flynn (1997)   (Correct)
16   Performance Optimization of VLSI Interconnect Layout - Cong, He, Koh, Madden (1996)   (Correct)
14   Vector Microprocessors - Asanovic (1998)   (Correct)
12   The Virtual Wires Emulation System: A Gate-Efficient ASIC Prototyping .. - Russell Tessier (1994)   (Correct)
12   Logic Emulation with Virtual Wires - Jonathan Babb (1997)   (Correct)
11   Minimum-Cost Bounded-Skew Clock Routing - Jason Cong (1995)   (Correct)
11   Comprehensive Lower Bound Estimation from Behavioral Descriptions - Seong Ohm Fadi (1994)   (Correct)
9   High-Level Test Generation Using Physically-Induced Faults - Hansen, Hayes (1995)   (Correct)
9   PERFORMANCE CHARACTERIZATION OF THE ALPHA 21164 MICROPROCESSOR USING.. - Cvetanovic, Bhandarkar (1996)   (Correct)
8   A Reversible Instruction Set Architecture and Algorithms - Hall (1994)   (Correct)
8   Path Optimization for Graph Partitioning Problems - Berry, Goldberg (1995)   (Correct)
8   The Design of An Asynchronous Communications Chip - Marshall, Coates, Siegel (1994)   (Correct)
8   Performance-Oriented Placement and Routing for Field-Programmable.. - Alexander, Cohoon, Ganley, Robins (1995)   (Correct)
8   The Design and Evaluation of an Asynchronous Microprocessor - Furber, Day, Garside, Paver, Temple, .. (1994)   (Correct)
8   A Genetic Algorithm for Channel Routing in VLSI Circuits - Lienig, Thulasiraman (1994)   (Correct)
7   A Gate-Level Leakage Power Reduction Method for Ultra-Low-Power CMOS.. - Halter (1997)   (Correct)
7   Optimizing Designs Containing Black Boxes - Aziz, Singhal (1997)   (Correct)
7   Design Issues In High Performance Floating Point Arithmetic Units - Oberman (1996)   (Correct)
6   An Electroid Switching Model for Reversible Computer Architectures - Hall (1993)   (Correct)
6   Verification of a Leader Election Protocol: Formal Methods Applied to .. - Devillers, Griffioen, Romijn.. (1997)   (Correct)
6   Pendulum: A Reversible Computer Architecture - Vieri (1995)   (Correct)
6   Decision Diagram Based Techniques for the Haar Wavelet Transform - Hansen, Sekine (1997)   (Correct)
6   Network Flow Based Circuit Partitioning for Time-multiplexed FPGAs - Liu (1998)   (Correct)
6   Technology Mapping for Electrically Programmable - Silvia Ercolani And (1991)   (Correct)
6   Three-Dimensional Field-Programmable Gate Arrays - Alexander, Cohoon, Colflesh, Karro.. (1995)   (Correct)
5   Estimation of Short-Circuit Power Dissipation for Static CMOS Gates - Hirata, Onodera, Tamaru (1995)   (Correct)
5   MOGAC: A Multiobjective Genetic Algorithm for Hardware-Software.. - Dick, Jha (1998)   (Correct)
5   The Genetic Algorithm as a Discovery Engine: Strange Circuits and New .. - Miller, Kalganova, Lipnitskaya, Job (1999)   (Correct)
5   Circuit Partitioning for Dynamically Reconfigurable FPGAs - Liu, Wong (1999)   (Correct)
4   Logic Design Error Diagnosis and Correction - Chung, Wang, Hajj (1994)   (Correct)
4   Dynamic Reordering in a Breadth-First Manipulation Based BDD Package: .. - Ranjan (1997)   (Correct)
4   Layout Synthesis Techniques for Yield Enhancement - Chiluvuri, Koren (1995)   (Correct)
4   An FPGA for Implementing Asynchronous Circuits - Hauck, Burns, Borriello, Ebeling (1994)   (Correct)
4   System-wide Energy Optimization in the MCM Environment - Burr, Burnham, Peterson (1991)   (Correct)
4   HSRA: High-Speed, Hierarchical Synchronous Reconfigurable Array - William Tsu (1999)   (Correct)
4   Net Partitions Yield Better Module Partitions - Jason Cong (1992)   (Correct)
4   Technology Mapping for a Two-Output RAM-Based Field Programmable Gate .. - Filo, Yang, Mailhot, De Micheli (1991)   (Correct)
4   Using Reconfigurable Computing Techniques to Accelerate Problems in.. - Zhong, Ashar, Malik, Martonosi (1998)   (Correct)
4   An Accurate Interconnection Length Estimation for Computer Logic - Stroobandt, Van Marck, Van Campenhout (1996)   (Correct)
4   A Fast Algorithm for Locating and Correcting Simple Design Errors in.. - Veneris, Hajj (1997)   (Correct)
4   Integration Of Logic Synthesis And High-Level Synthesis Into The.. - Perkowski, et.al (1989)   (Correct)
4   Adiabatic charging without inductors - Svensson, Koller (1994)   (Correct)
4   An Energy-Efficient CMOS Line Driver Using Adiabatic Switching - Athas, Koller, Svensson (1993)   (Correct)
4   A Method to Represent Multiple-Output Switching Functions by Using.. - Sasao (1996)   (Correct)
4   Computing Global Virtual Time in SharedMemory Multiprocessors - Richard Fujimoto And (2001)   (Correct)
4   Design-For-Debugging of Application Specific Designs - Miodrag Potkonjak Sujit (1995)   (Correct)
4   Improving Donath's technique for estimating the average.. - Stroobandt (1996)   (Correct)
4   Practical Verification And Synthesis Of Low Latency Asynchronous.. - Stevens (1994)   (Correct)
4   A Parallel Genetic Algorithm for Performance-Driven VLSI Routing - Lienig (1997)   (Correct)
3   An Engineering Approach to Formal Methods - Turner (1993)   (Correct)
3   LUT-Based FPGA Technology Mapping under Arbitrary Net-Delay Models - Cong (1994)   (Correct)
3   DILL: Specifying Digital Logic in LOTOS - Turner, Sinnott (1994)   (Correct)
3   An Evolutionary Robot Navigation System using a Gate-Level Evolvable.. - Keymeulen, Durantez, Konaka.. (1996)   (Correct)
3   Robot Learning using Gate-Level Evolvable Hardware - Keymeulen, Konaka, Iwata, Kuniyoshi, .. (1998)   (Correct)
3   A Floorplan Based Methodology for Data-Path Synthesis of Sub-micron.. - Moshnyaga, Tamaru (1996)   (Correct)
3   Testing Redundant Asynchronous Circuits by Variable Phase Splitting - Lavagno (1994)   (Correct)
3   Register Locking in an Asynchronous Microprocessor - Paver Day Furber (1992)   (Correct)
3   Design Error Diagnosis and Correction Via Test Vector Simulation - Veneris, Hajj (1999)   (Correct)
3   Parallel Programming with Logic Languages: a Survey - Ciancarini (1992)   (Correct)
3   Reasoning About Array Structures Using a Dependently Typed Logic - Dent, Hanna (1993)   (Correct)
3   A Comprehensive Estimation Technique for High-Level Synthesis - Seong Ohm Fadi (1995)   (Correct)
3   Top-Down Modeling of RISC Processors in VHDL - Juan (1993)   (Correct)
3   High Performance Carry Chains for FPGAs - Matthew Hosler Department (1998)   (Correct)
3   A Heuristic Algorithm to Design AND-OR-EXOR Three-Level Networks - Debnath (1998)   (Correct)
3   Formal Verification of Designs with Complex Control by Symbolic.. - Ritter, Eveking,, Hinrichsen (1999)   (Correct)
3   Accurate Area and Delay Estimation from RTL Descriptions - Srinivasan, Huber, LaPotin (1998)   (Correct)
3   Programmable Active Memories: the Coming of Age - Vuillemin, Bertin, Roncin, Shand.. (1994)   (Correct)
3   Symbolic Analysis of Large Analog Circuits with Determinant Decision.. - Shi, Tan (1997)   (Correct)
3   Configurable Computing: A Survey of Systems and Software - Compton, Hauck (1999)   (Correct)
2   A New Algorithm for Standard Cell Global Routing - Cong (1988)   (Correct)
2   Multi-level Logic Synthesis Based on Kronecker Decision Diagrams and.. - Perkowski, Schaefer, Sarabi.. (1995)   (Correct)
2   Effects of Technology Mapping on Fault Detection Coverage in.. - Kevin Kwiat (1995)   (Correct)
2   Minimal Logic Re-Synthesis For Engineering Change - Swamy (1997)   (Correct)
2   A Genetic Algorithm For Vlsi Physical Design Automation - Schnecke, Vornberger (1996)   (Correct)
2   A Data Parallel Algorithm for Boolean Function Manipulation - Gai, Rebaudengo, Reorda (1995)   (Correct)
2   Nuprl and its Use in Circuit Design - Jackson (1992)   (Correct)
2   On the decomposition of real-valued functions - Ross (1994)   (Correct)
2   Placement and Routing for Three-Dimensional FPGAs - Alexander, Cohoon, Colflesh, Karro.. (1996)   (Correct)
2   Performance Driven Synthesis for Pass-Transistor Logic - Liu, Aziz, Burns (1998)   (Correct)
2   Modelling Digital Logic in SDL - Csopaki (1997)   (Correct)
2   Delay Bounded Minimum Steiner Tree Algorithms for Performance-Driven.. - Zhu (1993)   (Correct)
2   A Case Study in Software Safety Assurance Using Formal Methods - Brenton Atchison Peter (1999)   (Correct)
2   Embedded DRAM for a Reconfigurable Array - Perissakis (1999)   (Correct)
2   Estimation of Short-Circuit Power Dissipation for Static CMOS Gates.. - Akio Hirata Hidetoshi (1996)   (Correct)
2   False Path Exclusion in Delay Analysis of RTL-Based.. - Nourani (1996)   (Correct)
2   The Cameron Project: High-Level Programming of Image Processing.. - Najjar, Draper, Böhm, Beveridge (1998)   (Correct)
2   The Design of a Register Renaming Unit - Bishop, Kelliher, Irwin (1999)   (Correct)
2   Optimal Design of Synchronous Circuits Using Software Pipelining.. - Francois Boyer And (1998)   (Correct)
2   False Path Exclusion in Delay Analysis of RTL-Based Datapath.. - Nourani, Papachristou (1996)   (Correct)
2   Implementation of the Veritas Design Logic - Hanna, Daeche, Howells (1992)   (Correct)
2   Bounded-Skew Clock and Steiner Routing - Cong, Kahng, Koh, Tsao (1999)   (Correct)
2   Digital Neurochip Design - Burr (1991)   (Correct)
2   Incremental Methods for Formal Verification and Logic Synthesis - Swamy (1996)   (Correct)
2   Effects of Technology Scaling on Area-Delay Characteristics of RTL.. - Moshnyaga, Tamaru (1997)   (Correct)
2   Rapid Prototyping of Microelectronic Systems - Dollas, Babcock (1995)   (Correct)
2   Software Technologies for Reconfigurable Systems - Hauck, Agarwal (1996)   (Correct)
2   Channel and Switchbox Routing with Minimized Crosstalk - A Parallel.. - Lienig (1997)   (Correct)
1   Simplification of Many-Valued Logic Formulas Using Anti-Links - Bernhard Beckert, Reiner Hähnle.. (1997)   (Correct)
1   Post-Layout Logic Restructuring for Performance Optimization - Jiang (1997)   (Correct)
1   Estimation of Propagation Delay considering Short-Circuit Current for .. - Hirata, Onodera, Tamaru (1998)   (Correct)
1   Vhdl-Based Simulation Of Electronic Circuits And Systems - Tavangarian (1995)   (Correct)
1   Evaluating benefits of Globally Asynchronous Locally Synchronous VLSI .. - Meincke, Hemani, Kumar, Ellervee.. (1998)   (Correct)
1   Multiple-Valued Combinational Circuits Synthesised Using Evolvable.. - Miller   (Correct)
1   Description of Timing Problems Using Petri Nets for Level-Independent .. - Altenbernd, Milczewski (1993)   (Correct)
1   High-Performance Visual Programming Environments: Goals and.. - Frost (1995)   (Correct)
1   Multiple Design Error Diagnosis and Correction in Digital VLSI.. - Veneris, al. (1999)   (Correct)
1   Table Transformation Tools: Why and How - Shen, Zucker, Parnas (1996)   (Correct)
1   Biologically-based Auditory Signal Processing in Analog VLSI - Lazzaro   (Correct)
1   Off-line Evolution for a Robot Navigation System based on a.. - Didier Keymeulen (1997)   (Correct)
1   Superconducting Processors for HTMT: Issues and Challenges - Kevin Theobald (1999)   (Correct)
1   Power-Pro: Programmable Power Management Architecture - Ishihara, Yasuura (1998)   (Correct)
1   Estimating interconnection lengths in three-dimensional computer.. - Stroobandt, VAN CAMPENHOUT (1997)   (Correct)
1   FPGA Based Low Cost Generic Reusable Module for the Rapid Prototyping .. - Dollas, Ward, Babcock (1994)   (Correct)
1   True Single-Phase Energy-Recovering Logic for Low-Power, High-Speed.. - Kim, Papaefthymiou (1998)   (Correct)
1   Canonical Symbolic Analysis of Large Analog Circuits with Determinant .. - Richard Shi Member (2000)   (Correct)
1   Use of Evolutionary Techniques to Automate the Design of.. - Coello, Christiansen, Aguirre (1999)   (Correct)
1   The Use of Petri Nets for the Design and Verification of Asynchronous .. - Kondratyev, Cortadella, Kishinevsky, .. (1998)   (Correct)
1   Toward in vivo Digital Circuits - Weiss, Homsy, Knight, Jr. (1999)   (Correct)
1   IDEA as a Benchmark for Reconfigurable Computing - Caspi, Weaver (1996)   (Correct)
1   Design Optimization Based on Diagnosis Techniques - Veneris, al. (2000)   (Correct)
1   Area-Optimized Technology Mapping for Hybrid FPGAs - Srini Krishnamoorthy Sriram (2000)   (Correct)
1   Statechart Methodology for the Design, Validation, and Synthesis of.. - Kol, Ginosar, Samuel (1996)   (Correct)
1   Functional Verification of a Multiple-issue, Out-of-Order.. - Taylor, Quinn, Brown, Dohm.. (1998)   (Correct)
1   Reprogrammable hardware for educational purposes - Gschwind (1994)   (Correct)
1   Using Garbage Collection in Model Checking - Iosif, Sisto (2000)   (Correct)
1   Solving Satisfiability Problems using Field Programmable Gate Arrays: .. - Yokoo (1996)   (Correct)
1   Test Session Oriented Built-in Self-testable Data Path Synthesis - Han Bin Kim (1998)   (Correct)
1   Asynchronous Embryonics with Reconfiguration - Alexander Jackson Andrew (2001)   (Correct)
1   C5M - A Control-Logic Layout Synthesis System for High-Performance.. - Burns, Feldman (1998)   (Correct)
1   Physical Design of VLSI Circuits and the Application of Genetic.. - Lienig (1997)   (Correct)
1   Efficient Implementation of a Planar Clock Routing with the Treatment .. - Kim, Zhou (1998)   (Correct)
1   An Interconnect-Centric Design Flow for Nanometer Technologies - Jason Cong Department (1999)   (Correct)
1   Digital Neural Network Implementations - Burr (1995)   (Correct)
1   Path Optimization and Near-Greedy Analysis for Graph Partitioning: An .. - Berry, Goldberg (1995)   (Correct)
1   Language Extensions for Semantic Integration of Deductive Databases - Asirelli, Renso, Turini (1996)   (Correct)
1   A Media-Enhanced Vector Architecture for Embedded Memory Systems - Kozyrakis (1999)   (Correct)
1   An Implicit Connection Graph Maze Routing Algorithm for ECO Routing - Jason Cong Jie (1999)   (Correct)
1   An Optimization of AND-OR-EXOR Three-Level Networks - Debnath, Sasao (1997)   (Correct)
1   Programming Architectures For Run-Time Reconfigurable Systems - Compton (1999)   (Correct)
1   Asynchronous Embryonics - Jackson, Tyrrell (2001)   (Correct)
1   An Indexed Bibliography of Genetic Algorithms in Electronics and VLSI .. - Alander (1999)   (Correct)
Basic Science and Challenges in Process Simulation - Dabrowski, Mussig, Duane, Dunham.. (1999)   (Correct)
New Directions in Software Safety: CAUSAL MODELLING as an Aid to.. - Fenelon, McDermid   (Correct)
Rich Brown, John Hayes, Trevor Mudge - Advanced Computer   (Correct)
A Survey on Parallel Logic Simulation - Meister (1993)   (Correct)
theoremTheorem[section] exampleExample[section].. - Em Ma   (Correct)
Towards OM - An Object-Oriented Implementation of Mantra - Butler, Kharma   (Correct)
Photon Structure Functions and Azimuthal Correlations from Lepton.. - Collisions Th   (Correct)
A BDD-based Verification Engine for Combinational Equivalence Checking - van Eijk (1997)   (Correct)
Applying Genetic Algorithms to the State Assignment Problem: A case.. - Jose Nelson   (Correct)
Anthony J. McAuley Bellcore (Room MRE-2N263), 445 South Street.. - Re Com   (Correct)
Minimal Logic Re-synthesis - Gitanjali Swamy (1994)   (Correct)
InnerView Hardware Debugger: A Logic Analysis Tool for the Virtual.. - Silvina Zimi   (Correct)
PLATO_P: PLA Timing Optimization by Partitioning - Despain, Liu (1995)   (Correct)
A Rough Logic Formalism for Fuzzy Controllers: A Hard and Soft.. - Lin (1996)   (Correct)
Cellular Automata and Artificial Life - Computation and Life in.. - Morita (1998)   (Correct)
subtract) the value of CO should be computed as the carry from the.. - Ci Inc   (Correct)
Computational Experience With A Primal-Dual Interior Point Method For .. - Kennings, Frazer, Vannelli   (Correct)
Boolean Manipulation with Free BDDs. An Application in Combinational.. - Gergov, Meinel (1994)   (Correct)
Reconfigurable Meshes: Theory and Practice - Bondalapati, Prasanna (1997)   (Correct)
Asynchronous Counters for Low Power Applications - Rutten And   (Correct)

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