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Abstract: The trace cache is a recently proposed solution to achieving high instruction fetch bandwidth by buffering and reusing dynamic instruction traces. This work presents a new block-based trace cache implementation that can achieve higher IPC performance with more efficient storage of traces. Instead of explicitly storing instructions of a trace, pointers to blocks constituting a trace are stored in a much smaller trace table. The block-based trace cache renames fetch addresses at the basic block... (Update)
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18: Trace Cache: A Low Latency Approach to High Bandwidth Instruction Fetching - Rotenberg, Bennett et al. - 1996
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BibTeX entry: (Update)
Bryan Black, Bohuslav Rychlik, and John Paul Shen. The block-based trace cache. Proceedings of the 26th Annual Intl. Symposium on Computer Architecture, May 1999. http://citeseer.ist.psu.edu/92664.html More
@inproceedings{ black99,
author = "Bryan Black and Bohuslav Rychlik and John Paul Shen",
institution = "Department of Electrical and Computer Engineering,
Carnegie Mellon University, Pittsburgh, USA",
title = "The Block-based Trace Cache",
year = 1999,
pages = "196--207",
booktitle = "Proceedings of the 26th Annual Intl. Symposium on Computer Architecture",
month = may,
publisher = "IEEE Computer Society Press",
url = "citeseer.ist.psu.edu/92664.html" }
Citations (may not include all citations):214 Combining Branch Predictors - McFarling - 1993
183 Trace Cache: A Low Latency Approach to High Bandwidth Instru.. - Rotenberg, Bennett et al. - 1996
125 Trace Processors - Rotenberg, Jacobson et al. - 1997
110 Improving the Accuracy of Dynamic Branch Prediction Using Br.. (context) - Pan, So et al. - 1992
93 Optimization of Instruction Fetch Mechanisms for High Issue .. - Conte, Menezes et al. - 1995
75 Increasing the Instruction Fetch Rate via Multiple Branch Pr.. - Yeh, Marr et al. - 1993
54 Dynamic Path-based Branch Correlation (context) - Nair - 1995
40 MultipleBlock Ahead Branch Predictors - Seznec, Jourdan et al. - 1996
39 Path-based Next Trace Prediction - Jacobson, Rotenberg et al. - 1997
36 PowerPC 604 RISC Microprocessor User's Manual (context) - Division - 1994
29 Next Cache Line and Set Prediction - Calder, Grunwald - 1995
25 Increasing the Instruction Fetch Rate via Block-structured I.. - Hao, Chang et al. - 1997
24 The PowerPC 604 RISC Microprocessor (context) - Song, Denman et al. - 1994
23 Calibration of Microprocessor Performance Models - Black, Shen - 1998
18 The Effects of Mispredicted-Path Execution on Branch Predict.. (context) - Jourdan, Hsing et al. - 1996
18 Enhancing Instruction Scheduling with a Block-Structured ISA (context) - Melvin, Patt - 1995
15 Alternative Fetch and Issue Policies for the Trace Cache Fet.. - Friendly, Patel et al. - 1997
12 The PowerPC User Instruction Set Architecture (context) - Diefendorf, Silha - 1994
10 Multiple Branch and Block Prediction - Wallace, Bagherzadeh - 1997
The graph only includes citing articles where the year of publication is known.
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