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Abstract: As microprocessor technology continues to scale into the nanometer regime, recent studies show that interconnect delay will be a limiting factor for performance, and multiple cycles will be necessary to communicate global signals across the chip. Thus, longer interconnects need to be pipelined, and the impact of the extra latency along wires needs to be considered during early micro-architecture design exploration. In this paper, we address this problem and make the following contributions: (1) ... (Update)
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BibTeX entry: (Update)
@misc{ pipelining-microarchitecture,
author = "And Interconnect Pipelining",
title = "Microarchitecture Evaluation With Floorplanning",
url = "citeseer.ist.psu.edu/766416.html" }
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