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Abstract: For multigigahertz designs in nanometer technologies, data transfers on global interconnects take multiple clock cycles. In this paper, we propose a regular distributed register (RDR) microarchitecture, which offers high regularity and direct support of multicycle on-chip communication. The RDR microarchitecture divides the entire chip into an array of islands so that all local computation and communication within an island can be performed in a single clock cycle. Each island contains a... (Update)
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BibTeX entry: (Update)
@misc{ jason-architecture,
author = "Multicycle Communication Jason",
title = "Architecture and Synthesis for On-Chip",
url = "citeseer.ist.psu.edu/766231.html" }
Citations (may not include all citations):320 Mediabench: A tool for evaluating and synthesizing multimedi.. - Lee, Potkonjak et al. - 1997
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104 for Semiconductors, Semiconductor Industry Association (context) - Technology - 1997
80 A fast computational algorithm for the discrete cosine trans.. (context) - Chen, Smith et al. - 1977
62 The multicluster architecture: Reducing cycle time through p.. - Farkas, Jouppi et al. - 1997
40 Dynamic critical-path scheduling: An effective technique for.. - Kwok, Ahmad - 1996 DBLP
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28 Globally-asynchronous locally-synchronous systems (context) - Chapiro - 1984
17 An introduction to machine SUIF and its portable libraries f.. (context) - Smith, Holloway - 2002
17 Physical planning with retiming - Cong, Lim - 2000 ACM DBLP
16 Timing-driven placement for FPGAs - Marquardt, Betz et al. - 2000
16 Understanding retiming through maximum average -delay cycles - Papaefthymiou - 1994
14 3D scheduling: High-level synthesis with floorplanning (context) - Weng, Parker - 1991
13 VLSI architecture: Past, present and future (context) - Dally, Lacy - 1999
12 for Semiconductors, Semiconductor Industry Association (context) - Roadmap - 2001
10 Simultaneous functional-unit binding and floorplanning (context) - Fang, Wong - 1994 ACM
10 Layout-driven RTL binding techniques for high-level synthesi.. (context) - Xu, Kurdahi - 1996
9 Optimum and heuristic transformation techniques for simultan.. - Srivastava, Potkonjak - 1995 ACM
7 Interconnect performance estimation models for design planni.. - Cong, Pan - 2001
6 Integrated retiming and placement for field programmable gat.. (context) - Singh, Brown - 2002 ACM DBLP
6 FPGA synthesis with retiming and pipelining for clock period.. - Cong, Wu - 1997 ACM DBLP
5 Multilevel global placement with retiming - Cong, Yuan - 2003 ACM DBLP
4 Architectural synthesis integrated with global placement for.. (context) - Cong, Fan et al. - 2003
4 Characterization of feasible retimings (context) - Chong, Brayton - 2001
4 High-level synthesis under multi-cycle interconnect delay (context) - Jeon, Kim et al. - 2001
4 Behavior-to-placed RTL synthesis with performance-driven pla.. (context) - Kim, Jung et al. - 2001 ACM DBLP
4 Regular fabrics in deep sub-micron integrated -circuit desig.. (context) - Mo, Brayton - 2002
3 Timing closure based on physical hierarchy - Cong - 2002 ACM DBLP
3 Layout-driven resource sharing in high-level synthesis (context) - Um, Kim et al. - 2002 ACM DBLP
2 Architecture and synthesis for multi-cycle communication - Cong, Fan et al. - 2003
2 Methodologies and tools for pipelined on-chip interconnect (context) - Scheffer - 2002 ACM DBLP
2 Parallel algorithms for simultaneous scheduling, binding and.. - Prabhakaran, Banerjee - 1998
2 ason Cong (S'88--M'90--SM'96--F'00) received the B (context) - Compiler, Available et al. - 1985
http://poppy.snu.ac.kr/CDFG
http://momonga.t.utokyo
http://www.altera.com
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