Pre-defined Dual-Vdd/Dual-Vt Fabrics Fei Li, Yan Lin, Lei He and Jason Cong ...  Home/Search
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Abstract: Traditional FPGAs use uniform supply voltage Vdd and uniform threshold voltage Vt. We propose to use pre-defined dual-Vdd and dual-Vt fabrics to reduce FPGA power. We design FPGA circuits with dual-Vdd/dual-Vt to e#ectively reduce both dynamic power and leakage power, and define dual-Vdd/dual-Vt FPGA fabrics based on the profiling of benchmark circuits. We further develop CAD algorithms including power-sensitivity based voltage assignment and simulated-annealing based placement to leverage... (Update)
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1.6: Low-Power FPGA Using Pre-defined Dual-Vdd/Dual-Vt Fabrics - Li, Lin, He, Cong (2004) (Correct)
0.6: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI).. - Fujio Ishihara Farhana (Correct)
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BibTeX entry: (Update)
@misc{ dual-vt-lowpower,
author = "Pre-Defined Dual-Vdd Dual-Vt",
title = "Low-Power FPGA Using",
url = "citeseer.ist.psu.edu/766129.html" }
Citations (may not include all citations):372 SIS: A system for sequential circuit synthesis - Sentovich - 1992
103 Physics of Semiconductor Devices (context) - Sze - 1981
59 TILOS: A posynomial programming approach to transistor sizin.. (context) - Fishburn, Dunlop - 1985
54 Architecture and CAD for Deep-Submicron FPGAs (context) - Betz, Rose et al. - 1999
35 Clustered voltage scaling techniques for low-power design (context) - Usami, Horowitz - 1995
35 RASP: A general logic synthesis system for SRAM-based FPGAs - Cong, Peck et al. - 1996
26 Automated low-power technique exploiting multiple supply vol.. (context) - Usami - 1998
17 Low-energy embedded FPGA structures (context) - Kusse, Rabaey - 1998
16 Dual-Threshold Voltage Techniques for Low-Power Digital Circ.. - Kao, Chandrakasan - 2000
10 Managing power and performance for system-on-chip designs us.. (context) - Lackey - 2002
9 Pushing ASIC performance in a power envelope - Puri - 2003
9 Methods for true power minimization - Brodersen - 2002
8 Utilizing surplus timing for power reduction (context) - Hamada, Ootaguro et al. - 2001
7 On gate level power optimization using dual-supply voltages - Chen, Srivastava et al. - 2001
7 A top-down low power design technique using clustered voltag.. (context) - Hamada - 1998
6 Architecture evaluation for power-e#cient fpgas (context) - Li, Chen et al. - 2003
5 FPGA power reduction using configurable dual-Vdd - Li, Lin et al. - 2003
4 Level conversion for dual-supply systems (context) - Ishihara, Sheikh et al. - 2003
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