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Abstract: We present a performance-driven programmable logic array mapping algorithm (PLAmap) for complex programmable logic device architectures consisting of a large number of PLA-style logic cells. The primary objective of the algorithm is to minimize the depth of the mapped circuit. We also develop several techniques for area reduction, including threshold control of PLA fanouts and product terms, slack-time relaxation, and PLA packing. We compare PLAmap with a previous algorithm TEMPLA (Anderson and ... (Update)
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4.7: Performance-Driven Mapping for CPLD Architectures - Chen, Cong, Ercegovac, Huang (2003) (Correct)
0.4: Technology Mapping and Architecture - Evalution For Macrocell-Based (Correct)
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BibTeX entry: (Update)
@misc{ jason-short,
author = "Deming Chen Jason",
title = "Short Papers_______________________________________________________________________________
Performance-Driven Mapping for CPLD Architectures",
url = "citeseer.ist.psu.edu/765856.html" }
Citations (may not include all citations):372 SIS: A System for Sequential Circuit Synthesis - Sentovich - 1992
98 FlowMap: An optimal technology mapping algorithm for delay o.. - Cong, Ding - 1994
59 IEEE Trans (context) - area, in et al. - 1994
45 Chortle-crf: Fast technology mapping for lookup table-based .. (context) - Francis, Rose et al. - 1991
41 DAG-Map: Graph-based FPGA technology mapping for delay optim.. - Chen, Cong et al. - 1992
24 Module clustering to minimize delay in digital networks (context) - Lawler, Levitt et al. - 1969
16 Structural gate decomposition for depth-optimal technology i.. - Cong, Huang - 2000
4 The Lattice Data Book, Lattice Semiconductor Corporation (context) - Data, Semiconductor - 2000
3 Empirical Study of the Effect of Cell Granularity on FPGA De.. (context) - Kouloheris - 1993
2 PLATO P : PLA timing optimization by partitioning (context) - Liu, Pedram et al. - 1995
2 A fast partition method for PLA-based FPGA's (context) - Hasan, Harrison et al. - 1992
2 Canada: McGraw-Hill (context) - Micheli, Optimization et al. - 1994
2 A technology mapping algorithm for PAL-based devices using m.. (context) - Kania - 2000
2 Technology mapping for large complex PLD's (context) - Anderson, Brown - 1998
2 A new technology mapping for CPLD under the time constraint (context) - Kim, Kim et al. - 2001
2 Technology mapping for k/mmacrocell based FPGA's (context) - Cong, Huang et al. - 2000
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