Low Overhead Off-Chip Caches Zhao Zhang, Member, IEEE, Zhichun Zhu, Member,...  Home/Search
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Abstract: Large off-chip L3 caches can significantly improve the performance of memory-intensive applications. However, conventional L3 SRAM caches are facing two issues as those applications require increasingly large caches. First, an SRAM cache has a limited size due to the low density and high cost of SRAM and, thus, cannot hold the working sets of many memory-intensive applications. Second, since the tag checking overhead of large caches is nontrivial, the existence of L3 caches increases the... (Update)
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BibTeX entry: (Update)
@misc{ off-chip-design,
author = "Low Overhead Off-Chip",
title = "Design and Optimization of Large Size and",
url = "citeseer.ist.psu.edu/765612.html" }
Citations (may not include all citations):443 Improving Direct-Mapped Cache Performance by the Addition of.. - Jouppi - 1990
147 Alternative Implementations of TwoLevel Adaptive Branch Pred.. - Yeh, Patt - 1992
131 Parallel Computer Architecture HardwareSoftware Approach (context) - Singh, Computer et al. - 1999
98 Evaluating Stream Buffers as a Secondary Cache Replacement (context) - Palacharla, Kessler - 1994
52 A Modified Approach to Data Cache Management - Tyson, Farrens et al. - 1995
47 A Performance Comparison of Contemporary DRAM Architectures - Cuppu, Jacob et al. - 1999
45 A Case for Intelligent RAM - Patterson, Anderson et al. - 1997
40 the Inclusion Properties for MultiLevel Cache Hierarchies (context) - Baer, Wang - 1988
37 Tolerating Memory Latency through Software-Controlled Pre-Ex.. - Luk - 2001
29 The Design and Analysis of a Cache Architecture for Texture .. (context) - Hakura, Gupta - 1997
28 Data Prefetching by Dependence Graph Precomputation - Annavaram, Patel et al. - 2001
25 Missing the Memory Wall: The Case for Processor/Memory Integ.. (context) - Saulsbury, Pong et al. - 1996
23 Speculation Techniques for Improving Load Related Instructio.. - Yoaz, Erez et al. - 1999
22 Performance of Cached DRAM Organizations in Vector Supercomp.. (context) - Hsu, Smith - 1993
18 Reducing DRAM Latencies with an Integrated Memory Hierarchy .. - Lin, Reinhardt et al. - 2001
16 Dynamically Allocating Processor Resources between Nearby an.. - Balasubramonian, Dwarkadas et al. - 2001
15 Decoupled Sectored Caches: Conciliating Low Tag Implementati.. - Seznec - 1994
12 DCD-Disk Caching Disk: A New Approach for Boosting I/O Perfo.. - Hu, Yang - 1996
12 A New Era of Fast Dynamic RAMs (context) - Jones - 1992
12 Performance of Hardware Compressed Main Memory - Abali, Franke et al. - 2001
10 A Study of Instruction Cache Organization and Replacement Po.. (context) - Smith, Goodman - 1983
9 Modified LRU Policies for Improving Second-Level Cache Behav.. (context) - Wong, Baer - 2000
8 AlphaServer 4100 Performance Characterization (context) - Cvetanovic, Donaldson - 1996
8 CACTI 3.0: An Integrated Cache Timing, Power, and Area Model (context) - Shivakumar, Jouppi - 2001
8 System-Level Implications of Processor-Memory Integration - Burger - 1997
6 The Cache DRAM Architecture: A DRAM with an On-Chip Cache Me.. (context) - Hidaka, Matsuda et al. - 1990
6 A Permutation-Based Page Interleaving Scheme to Reduce Row-B.. - Zhang, Zhu et al. - 2000
5 Pinnacle: IBM MXT in a Memory Controller Chip (context) - Tremaine, Smith et al. - 2001
5 CDRAM in a Unified Memory Architecture (context) - Hart - 1994
5 The Architecture of the DIVA Processing-in-Memory Chip - Draper, Chame et al. - 2002
5 Eager Writeback---A Technique for Improving Bandwidth Utiliz.. - Lee, Tyson et al. - 2000
4 Designing High Bandwidth OnChip Caches (context) - Wilson, Olukotun - 1997
4 A Media-Enhanced Vector Architecture for Embedded Memory Sys.. - Kozyrakis - 1999
3 Functional Implementation Techniques for CPU Cache Memories (context) - Peir, Hsu et al. - 1999
3 A Single Chip Multiprocessor Integrated with High Density DR.. - Yamauchi, Hammond et al. - 1997
3 Multi-Level Texture Caching for 3D Graphics Hardware (context) - Cox, Bhandari et al. - 1998
2 An Equal Area Comparison of Embedded DRAM and SRAM Memory Ar.. - Keltcher, Richardson et al. - 2000
2 white paper (context) - System - 2001
2 WCDRAM: A Fully Associative Integrated Cached-DRAM with Wide.. - Koganti, Kedem - 1997
2 Bloom Filtering Cache Misses for Accurate Data Speculation a.. (context) - Peir, Lai et al. - 2002
2 A Decoupled Predictor-Directed Stream Prefetching Architectu.. (context) - Sherwood, Calder - 2003
1 The IA-64 Itanium Processor Cartridge (context) - Samaras, Cherukuri et al. - 2001
1 Memory-Intensive Benchmarks: IRAM vs. Cache-Based Machines - Gaeke, Husbands et al. - 2002
1 Fine-Grain Priority Scheduling on Multi-Channel Memory Syste.. - Zhu, Zhang et al. - 2002
1 Mit ESDRAM Components (context) - Systems - 2000
1 Cached DRAM: A Simple and Effective Technique for Memory Acc.. (context) - Zhang, Zhu et al. - 2001
1 DRAM On-Chip Caching (context) - Wong, Baer - 1997
1 Active Memory: Micron's Yukon (context) - Kirsch - 2003
1 Vector IRAM: A MediaEnhanced Vector Processor with Embedded .. (context) - Kozyrakis, Gebis et al. - 2000
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