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Abstract: Recently, design reuse has emerged as a dominant integrated system design and integration paradigm. However, the intellectual property (IP) business model is vulnerable to a number of potentially devastating obstructions, such as misappropriation and intellectual property fraud. We propose a new method for IP protection (IPP) which facilitates design watermarking at the combinational logic synthesis level. We developed protocols for embedding designer- and/or tool-specific information into a... (Update)
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BibTeX entry: (Update)
@misc{ synthesis-intellectual,
author = "Combinational Logic Synthesis",
title = "Intellectual Property Protection By Watermarking",
url = "citeseer.ist.psu.edu/765472.html" }
Citations (may not include all citations):1065 Handbook of applied cryptography (context) - Menezes, van Oorschot et al. - 1997
212 Techniques for data hiding (context) - Bender - 1996
171 Synthesis and optimization of digital circuits (context) - De Micheli - 1994
150 MIS: a multiple-level logic optimization system (context) - Brayton - 1987
115 Low cost attacks on tamper resistant devices - Anderson, Kuhn - 1998
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43 Kluwer Academic Publishers (context) - Hachtel, Somenzi et al. - 1996
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12 A survey of Boolean matching techniques for library binding - Benini, De Micheli - 1997
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8 Optimizing Designs Containing Black Boxes - Liu - 1997
8 On synthesis-for-testability of combinational logic circuits (context) - Pomeranz, Reddy - 1995
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