Advances in processor design have led to the development of Chip Multiprocessors (CMP) and Simultaneous Multithreading (SMT) processors that can exploit Thread-Level Parallelism (TLP) in suitably parallelized applications. The performance of these processors, however, largely depends on the programming model chosen for parallelization. For several important classes of applications, the commonly used spatial decomposition model of parallelism leads to inefficient usage of the memory hierarchy on these processors because of increased cache misses and memory bus utilization, causing the applications to perform poorly. As an alternative, we propose the Synchronized Pipelined Parallelism Model (SPPM) for parallelizing such applications on these processors. SPPM restructures applications as a producer-consumer chain and utilizes the high inter-processor communication bandwidth — either in the form of a fast processor interconnect, or one or more shared cache levels — on these multipro-cessor systems for communication between threads. SPPM is also effective on conventional Symmetric Multiprocessor (SMP) systems that have a high-speed front-side bus. In this paper, we demonstrate that SPPM provides better performance than the spatial decomposition model on these processors for the target applications, while maintaining the overall cache miss rate and, consequently, the memory bus utilization at around the same levels as those in the original sequential applications. rency.
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