Suresh Srinivasan, Prasanth Mangalagiri, Yuan Xie, N. Vijaykrishnan Dept. of...  Home/Search
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Abstract: Aggressive scaling of technology has an adverse impact on the reliability of VLSI circuits. Apart from increasing transient error susceptibility, the circuits also become more vulnerable to permanent damage and failures due to different physical phenomenon. Such concerns have been recently demonstrated for regular microarchitectures. In this work we demonstrate the vulnerability of Field Programmable Gate Arrays (FPGA)s to two different types of hard errors, namely, Time Dependent Dielectric... (Update)
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BibTeX entry: (Update)
@misc{ prasanth-flaw,
author = "Suresh Srinivasan Prasanth",
title = "FLAW: FPGA Lifetime AWareness",
url = "citeseer.ist.psu.edu/751027.html" }
Citations (may not include all citations):40 Transition density, a stochastic measure of activity in digi.. - Najm - 1991
34 VPR: A new packing, placement and routing tool for FPGA rese.. - Betz, Rose - 1997
14 JRoute: A Run-Time Routing API for FPGA Hardware - Keller - 2000
6 Reliability limits for the Gate Insulator in CMOS Technology (context) - Stathis - 2002
4 Active leakage power optimization for FPGAs - Anderson, Najm et al. - 2004
3 The Impact of Technology Scaling on Lifetime Reliability - Srinivasan, Adve et al. - 2004
2 The threshold-voltage model of MOSFET devices with localized.. (context) - Jean, Wu - 1997
1 Performance and hot-carrier reliability of 100 nm channel le.. (context) - Mahapatra, Rao et al. - 2001
1 Leakage control in FPGA routing fabric (context) - Srinivasan, Gayasen et al. - 2005
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1 the International Technology Roadmap for Semiconductors" In .. (context) - Challenges - 2003
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