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Abstract:

In recent years the field of Artificial Neural Networks has continued to mature, and presently many network architectures are understood fairly well. Research into new architectures continues, however, as (in particular) there is a need to increase the efficiency of network implementations, which would enable building larger and more complex systems. In fact, there exist networks possessing desirable computational properties (e.g., high speed of operation and implementational simplicity) that, at the same time, lack a comprehensive mathematical foundation of their operation and, consequently, heuristic rules are often applied when such networks are realized. In this work we attempt to provide are unifying description of a class of neural network architectures whose operation relies on combining multiple (vector) quantization of the input space with simple memory look-up. Such networks essentially build their response by generating a fixed number of memory addresses for any possible input, and then combine the addressed memory locations (usually by summation) to provide the final network response. Provided that the address-generating part of network mapping can be realized efficiently, and when the number of addressed locations is relatively small, such networks are characterized by fast operation. Additionally, if the address-generating module has a fixed form during network training,

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