HARP: Hard-wired Routing Pattern FPGAs
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by Satish Sivaswamy, Gang Wang, Cristinel Ababei, Kia Bazargan, Ryan Kastner, Eli Bozorgzadeh
http://www.ics.uci.edu/~eli/publications/conference/p21-sivaswamy.pdf
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Abstract:
Modern FPGA architectures provide ample routing resources so that designs can be routed successfully. The routing architecture is designed to handle versatile connection configurations. However, providing such great flexibility comes at a high cost in terms of area, delay and power. We propose a new FPGA routing architecture 1 that utilizes a mixture of hardwired and traditional flexible switches. The result is 24 % reduction in leakage power consumption, 7 % smaller area and 24 % shorter delays, which translates to 30 % increase in clock frequency. Despite the increase in clock speeds, the overall power consumption is reduced by 8%.
Citations
| 180 | Architecture And CAD For Deep-Submicron FPGAs – Betz, Rose, et al. - 1999 |
| 145 | VPR: A new packing, placement and routing tool for FPGA research – Betz, Rose - 1997 |
| 81 | Reconfigurable Architectures for General-Purpose Computing – DeHon - 1996 |
| 28 | Universal switch modules for FPGA design – CHANG, WONG, et al. - 1996 |
| 16 | Active leakage power optimization for FPGAs – Anderson, Najm, et al. - 2004 |
| 9 | An Architecture-Driven Metric for Simultaneous Placement and Global Routing for FPGAs – Chang, Chang |
| 6 | T.Tuan. A dual vdd low power fpga architecture – Gayasen, Vijaykrishnan, et al. - 2004 |
| 5 | FPGA Routing Structures: A Novel Switch Block and Depopulated interconnect Matrix Architecture – Masud - 1999 |
| 2 | A METAL and VIA Maskset Programmable VLSI Design Methodology using PLAs – Jayakumar, Khatri - 2004 |
