Gate-level Power Estimation Using Tagged Probabilistic Simulation Chih-Shun...  Home/Search
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Abstract: In this paper, we present a probabilistic simulation technique to estimate the power consumption of a cmos circuit under a general delay model. This technique is based on the notion of tagged (probability) waveforms, which model the set of all possible events at the output of each circuit node. Tagged waveforms are obtained by partitioning the logic waveform space of a circuit node according to the initial and final values of each logic waveform and compacting all logic waveforms in each... (Update)
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BibTeX entry: (Update)
@misc{ estimation-revision,
author = "Gate-Level Power Estimation",
title = "Revision of Manuscript 42:",
url = "citeseer.ist.psu.edu/747236.html" }
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