Massoud Pedram, Qing Wu Dept. of Electrical Engineering-Systems University of ...  Home/Search
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Abstract: The logic construction of a double-edge-triggered (DET) flip-flop, which can receive input signal at two levels of the clock, is analyzed and a new circuit design of CMOS DET flip-flop is proposed. Simulation using SPICE and a 1 micron technology shows that this DET flip-flop has ideal logic functionality, a simpler structure, lower delay time and higher maximum data rate compared to other existing CMOS DET flipflops. By simulating and comparing the proposed DET flip-flop with the traditional... (Update)
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BibTeX entry: (Update)
@misc{ qing-new,
author = "Massoud Pedram Qing",
title = "A New Design for Double Edge Triggered Flip-flops*",
url = "citeseer.ist.psu.edu/747172.html" }
Citations (may not include all citations):159 Principles of CMOS VLSI Design: A System Perspective (context) - Weste, Eshraghian - 1993
102 Power minimization in IC Design: Principles and applications - Pedram - 1996
46 Accurate simulation of power dissipation in VLSI circuits (context) - Kang - 1986
20 Activity-driven clock design for low power circuits (context) - Tellez, Farrah et al. - 1995
9 Low power design using double edge triggered flip-flops (context) - Hossain, Wronski et al. - 1994
5 Double-edge-triggered flip-flops (context) - Unger - 1981
2 A novel CMOS implementation of double-edge-triggered flip-fl.. (context) - Lu, Ercegovac - 1990
2 Double edge-triggered D-flip-flops for highspeed circuits (context) - Afghahi, Yuan - 1991
2 Reduced implementation of Dtype DET flip-flops (context) - Gago, Escano et al. - 1993
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