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Abstract: We present an accurate model and procedures for predicting the common physical design characteristics of standard cell layouts (i.e., the interconnection length and the chip area). The predicted results are obtained from analysis of the net list only, that is, no prior knowledge of the functionality of the design is used. Random and optimized placements, global routing, and detailed routing are each abstracted by procedural models that capture the important features of these processes, and... (Update)
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BibTeX entry: (Update)
@misc{ bryan-interconnection,
author = "Massoud Pedram Bryan",
title = "Interconnection Analysis for Standard Cell Layouts",
url = "citeseer.ist.psu.edu/747016.html" }
Citations (may not include all citations):4212 Computers and Intractability: A Guide to the Theory of NP-co.. (context) - Garey, Johnson - 1979
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65 Interconnect scaling - the real limiter to high performance .. (context) - Bohr - 1995
30 Efficient Algorithms for Channel Routing (context) - Yoshimura, Kuh - 1982
25 A new algorithm for standard cell global routing - Cong, Preas - 1988
24 Layout driven technology mapping (context) - Pedram, Bhat - 1991
21 Techniques for area estimation of VLSI layouts (context) - Kurdahi, Parker - 1989
18 An improved simulated annealing algorithm for row-based plac.. (context) - Sechen, Lee - 1987
18 Two dimensional stochastic model for interconnections in mas.. (context) - Gamal - 1981
16 Interconnection length estimation for optimized standard cel.. (context) - Pedram, Preas - 1989
15 dogleg' channel router (context) - Deutsch - 1976
11 Average interconnection length estimation for random and opt.. (context) - Sechen - 1987
10 Benchmarks for cell-based layout systems (context) - Preas - 1987
6 The largest minimal rectilinear steiner trees for a set of n.. (context) - Chung, Hwang - 1979
6 A module area estimator for VLSI layout (context) - Chen, Bushnell - 1988
5 Accurate prediction of physical design characteristics of ra.. (context) - Pedram, Preas - 1989
4 Prediction of wiring space requirements for LSI (context) - Heller, Mikhail et al. - 1977
4 Stochastic models for wirability analysis of gate arrays (context) - Sastry, Parker - 1986
2 Patchwork: Layout from schematic notations (context) - Barth, Monier et al. - 1988
2 Hierarchical structure of computers (context) - Donath - 1969
1 Stochastic model of the computer logic design process (context) - Donath - 1970
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