See this document in CiteSeerX!

Optimistic Intra-Transaction Parallelism (2005)  (Make Corrections)  
on Chip Multiprocessors Christopher B. Colohan Anastassia Ailamaki J....



  Home/Search   Context   Related

 
View or download:
cmu.edu/anon/2005/CMUCS05118.ps
Cached:  PS.gz  PS  PDF   Image  Update  Help

From:  cmu.edu/anon/2005/ (more)
(Enter author homepages)

Rate this article: (best)
  Comment on this article  
(Enter summary)

Abstract: With the advent of chip multiprocessors, exploiting intra-transaction parallelism is an attractive way of improving transaction performance. However, exploiting intra-transaction parallelism in existing database systems is di#cult, for two reasons: first, significant changes are required to avoid races or conflicts within the DBMS, and second, adding threads to transactions requires a high level of sophistication from transaction programmers. In this paper we show how dividing a transaction... (Update)

Active bibliography (related documents):   More   All
1.1:   Tolerating Dependences Between Large Speculative.. - Christopher Colohan..   (Correct)
0.4:   Enhancing Software Reliability With Speculative Threads - And The Committee   (Correct)
0.4:   A Scalable Concurrent malloc(3) Implementation for FreeBSD - Evans (2006)   (Correct)

Similar documents based on text:
0.0:   Unknown -   (Correct)

BibTeX entry:   (Update)

@misc{ multiprocessors-optimistic,
  author = "On Chip Multiprocessors",
  title = "Optimistic Intra-Transaction Parallelism",
  url = "citeseer.ist.psu.edu/746311.html" }
Citations (may not include all citations):
334   Operating System Concepts (context) - Silberschatz, Galvin et al. - 2002
246   On optimistic methods for concurrency control (context) - Kung, Robinson - 1981
189   ARIES: A Transaction Recovery Method Supporting Fine-Granula.. (context) - Mohan, Haderle et al. - 1992
136   superscalar microprocessor (context) - Yeager - 1996
74   Transactional memory: Architectural support for lock-free da.. - Herlihy, Moss - 1993
74   Speculative Versioning Cache - Gopal, Vijaykumar et al. - 1998
50   Hoard: A Scalable Memory Allocator for Multithreaded Applica.. - Berger, McKinley et al. - 2000
20   MAJC: Microprocessor Architecture for Java Computing (context) - Tremblay - 1999
10   Intra-transaction parallelism in the mapping of an object mo.. - Rys, Norrie et al. - 1996
10   and Margo Seltzer (context) - Olson, Bostic - 1999
9   IBM DB2 Universal Database Administration Guide: Performance (context) - Corporation - 2004
6   The Benchmark Handbook for Transaction Processing Systems (context) - Gray - 1993
5   Using thread-level speculation to simplify manual paralleliz.. - Prabhu, Olukotun - 2003
5   Extending tp-monitors for intra-transaction parallelism (context) - Kaufmann, Schek - 1996
5   IEEE Micro Magazine (context) - Hammond, Hubbert et al. - 2000
4   A Scalable Approach to Thread-Level Speculation (context) - Ste, Colohan et al. - 2000
2   Extending Thread Level Speculation Hardware Support to Large.. (context) - Colohan, Ailamaki et al. - 2005
1   Microsoft SQL Server (context) - Miller, Lau - 2000
1   Personal communication (context) - Zuzarte - 2005

Documents on the same site (http://reports-archive.adm.cs.cmu.edu/anon/2005/):   More
Taxonomy and Effectiveness of Worm Defense Strategies - Brumley, Liu, Poosankam, Song (2005)   (Correct)
Learning To Prevent Failure State for a Dynamically.. - Searock, Browning, Veloso (2005)   (Correct)
Device-Enabled Authorization in the Grey System - Bauer, Garriss, McCune.. (2005)   (Correct)

Online articles have much greater impact   More about CiteSeer.IST   Add search form to your site   Submit documents   Feedback  

CiteSeer.IST - Copyright Penn State and NEC