Aravindh V. Anantaraman, Ali El-Haj Mahmoud, Ravi K. Venkatesan, Yifan Zhu...  Home/Search
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Abstract: Power consumption has become a major concern, both for processor design with high clock rates and embedded systems that rely on batteries to operate. Recent support for dynamic frequency and voltage scaling (DVS) in contemporary architectures allows software to affect power consumption by varying both execution frequency and supply voltage on the fly. However, processors generally enter a sleep state while transitioning between frequencies/voltages. In the following, we describe an experimental ... (Update)
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BibTeX entry: (Update)
@misc{ ali-edfdvs,
author = "Aravindh Anantaraman Ali",
title = "EDF-DVS Scheduling on the IBM Embedded PowerPC 405LP",
url = "citeseer.ist.psu.edu/744119.html" }
Citations (may not include all citations):304 Scheduler activations: Effective kernel support for the user.. - Anderson, Bershad et al. - 1992 DBLP
195 Scheduling for reduced cpu energy - Weiser, Welch et al. - 1994 DBLP
128 Comparing algorithms for dynamic speed-setting of a low-powe.. - Govil, Chan et al. - 1995
103 Real-time dynamic voltage scaling for low-power embedded ope.. - Pillai, Shin - 2001 ACM DBLP
94 A library implementation of POSIX threads under UNIX - Mueller - 1993 DBLP
64 SunOS multi-thread architecture - Powell, Kleiman et al. - 1991 DBLP
61 Integrating the timing analysis of pipelining and instructio.. (context) - Healy, Whalley et al. - 1995 ACM DBLP
56 Policies for dynamic clock scheduling - Grunwald, Levis et al. - 2000 DBLP
14 A comparison of static analysis and evolutionary testing for.. - Wegener, Mueller - 2001
9 Energy-conserving feedback edf scheduling for embedded syste.. - Dudani, Mueller et al. - 2002
8 Dynamic and agressive scheduling techniques for power-aware .. (context) - Aydin, Melhem et al. - 2001
6 Portable multithreading: the signal stack trick for user-spa.. - Engelschall - 2000
5 The simulation of dynamic voltage scaling algorithms (context) - Pering, Burd et al. - 1995
5 Preemption handling and scalability of feedback dvs-edf - Zhu, Mueller - 2002
3 A fast resource synthesis technique for energy-efficient rea.. (context) - Kang, Crago et al. - 2002 ACM
2 Dynamic power management for embedded systems (context) - Brock, Rajamani - 2003
2 TR CMU-CS (context) - Cooper, Draves et al. - 1988
1 The design and application of the powerpc 405lp energy-effic.. (context) - Nowka, Carpenter et al. - 2003
1 Dynamic power management for embedded systems - IBM
1 Feedback edf scheduling exploiting dynamic voltage scaling (context) - Zhu, Mueller - 2004 ACM
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