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Abstract: This dissertation presents methods for bounding the worstcase interference between an executing program and a cycle-stealing DMA I/O operation. We first develop a method for bounding the WCET of a program executing concurrently with cycle-stealing DMA I/O. Our method converts the problem of bounding the WCET to one of solving a integer linear programming problem. We implement our method in a timing tool and conduct extensive experiments with the timing tool to demonstrate the merits of our... (Update)
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BibTeX entry: (Update)
T.-Y. Huang, "Worst-case timing analysis of concurrently executing DMA I/O and programs," Ph.D. dissertation, Univ. Illinois, Dept. Computer Sci., Sept. 1996. http://citeseer.ist.psu.edu/article/huang97worst.html More
@techreport{ huang96worstcase,
author = "Tai-Yi Huang",
title = "Worst-Case Timing Analysis of Concurrently Executing {DMA} {I}/{O} and Programs",
number = "UIUCDCS-R-96-1978",
year = "1996",
url = "citeseer.ist.psu.edu/article/huang97worst.html" }
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