MetaCartSign in to MyCiteSeer

Include Citations | Advanced Search | Help

Include Citations | Advanced Search | Help

  Evaluation of Onchip Networks Using Deflection Routing (2006) [2 citations — 0 self]

Download:
pdf
by Zhonghai Lu
In Proc. 16th ACM Great Lakes Symposium on VLSI (GLSVLSI 2006
http://www.imit.kth.se/~axel/papers/2006/GLSVLSI-zhonghai-lu.pdf
Add To MetaCart

Abstract:

Deflection routing is being proposed for networks on chips since it is simple and adaptive. A deflection switch can be much smaller and faster than a wormhole or virtual cutthrough switch. A deflection-routed network has three orthogonal characteristics: topology, routing algorithm and deflection policy. In this paper we evaluate deflection networks with different topologies such as mesh, torus and Manhattan Street Network, different routing algorithms such as random, dimension XY, delta XY and minimum deflection, aswell as different deflection policies such as non-priority, weighted priority and straight-through policies. Our results suggest that the performance of a deflection network is more sensitive to its topology than the other two parameters. It is less sensitive to its routing algorithm, but a routing algorithm should be minimal. A priority-based deflection policy that uses global and history-related criterion can achieve both better average-case and worst-case performance than a non-priority or priority policy that uses local and stateless criterion. These findings are important since they can guide designers to make right decisions on the deflection network architecture, for instance, selecting a routing algorithm or deflection policy which has potentially low cost and high speed for hardware implementation.

Citations

245 Route packets, not wires: on-chip interconnection networks,” DAC - Design Automation Conference – Dally - 2001
110 System level design: orthogonalization of concerns and platform-based design – Keutzer, Malik, et al. - 2000
43 Guaranteed bandwidth using looped containers in temporally disjoint networks within the Nostrum network on chip – Millberg, Nilsson, et al. - 2004
32 Deterministic many-to-many hot potato routing – Borodin, Rabani, et al. - 1995
29 Bounds on maximum delay in networks with deflection routing – Brassil, Cruz - 1995
20 Sharp approximate models of deflection routing in mesh networks – Greenberg, Goodman - 1993
14 On-chip stochastic communication – Dumitras, Marculescu - 2003
11 Packetization and Routing Analysis of On-chip Multiprocessor Networks – Ye, Benini, et al. - 2004
5 The Connection Machine – Hills - 1985
5 Reducing peak power and latency in 2-D mesh NoCs using globally pseudochronous locally synchronous clocking – Nilsson, Öberg - 2004
4 On distributed computing networks – Baran - 1964
4 A study on the implementation of 2D mesh based networks on chip in the nanoregime – Pamunuwa, Öberg, et al. - 2004
2 Traffic configuration for evaluating networks on chips – Lu, Jantsch - 2005