(Enter summary)
Abstract: Transactional Coherence and Consistency (TCC) is a
novel coherence scheme for shared memory multiprocessors
that uses programmer-defined transactions as the fundamental
unit of parallel work, synchronization, coherence,
and consistency. TCC has the potential to simplify parallel
program development and optimization by providing a
smooth transition from sequential to parallel programs. (Update)
Cited by: More
TAPE: A Transactional Application Profiling Environment - Chi (2005)
(Correct)
The Common Case Transactional Behavior of Multithreaded.. - Jaewoong Chung Hassan (2006)
(Correct)
The Software Stack for Transactional Memory - Challenges And Opportunities (2006)
(Correct)
Active bibliography (related documents): More All
1.4: Transactional Execution of Java Programs - Brian Carlstrom Jaewoong (2005)
(Correct)
0.8: The System-on-a-Chip Lock Cache - Akgul (2004)
(Correct)
0.7: Building and Using the ATLAS Transactional Memory System - Njuguna Njoroge Sewook (2006)
(Correct)
Similar documents based on text:
0.0: Unknown -
(Correct)
Related documents from co-citation: More All
4: Unbounded transactional memory (context) - Ananian, Asanovic - 2005
4: Language support for lightweight transactions
- Harris, Fraser - 2003
4: Transactional memory coherence and consistency (context) - Hammond, Wong et al. - 2004
BibTeX entry: (Update)
A. McDonald, J. Chung, H. Chafi, C. Cao Minh, B. D. Carlstrom, L. Hammond, C. Kozyrakis, and K. Olukotun. Characterization of tcc on chip-multiprocessors. In Proceedings of the 14th International Conference on Parallel Architectures and Compilation Techniques, September 2005. http://citeseer.ist.psu.edu/739545.html More
@misc{ mcdonald05characterization,
author = "A. McDonald and J. Chung and H. Chafi and C. Minh and B. Carlstrom and
L. Hammond and C. Kozyrakis and K. Olukotun",
title = "Characterization of tcc on chip-multiprocessors",
text = "A. McDonald, J. Chung, H. Chafi, C. Cao Minh, B. D. Carlstrom, L. Hammond,
C. Kozyrakis, and K. Olukotun. Characterization of tcc on chip-multiprocessors.
In Proceedings of the 14th International Conference on Parallel Architectures
and Compilation Techniques, September 2005.",
year = "2005",
url = "citeseer.ist.psu.edu/739545.html" }
Citations (may not include all citations):
901
Transaction Processing: Concepts and Techniques (context) - Gray, Reuter - 1993
496
Splash: Stanford parallel applications for shared-memory (context) - Singh, Weber et al.
443
Improving direct-mapped cache performance by the addition of..
- Jouppi - 1990
353
The splash2 programs: Characterization and methodological co..
- Woo, Ohara et al. - 1995
269
Multiscalar processors
- Sohi, Breach et al. - 1995
246
On optimistic methods for concurrency control (context) - Kung, Robinson - 1981
159
LRPD test: Speculative runtime parallelization of loops with..
- Rauchwerger, Padua - 1995
156
An evaluation of directory schemes for cache coherence
- Agarwal, Hennessy et al. - 1988
155
Cache coherence protocols: Evaluation using a multiprocessor.. (context) - Archibald, Baer - 1986
111
Using cache memory to reduce processor memory traffic (context) - Goodman - 1983
86
The Jalapeno virtual machine (context) - Alpern, Attanasio et al. - 2000
77
The potential for using thread-level data speculation to fac..
- Steffan, Mowry - 1998
74
Transactional memory: Architectural support for lock-free da..
- Herlihy, Moss - 1993
74
Speculative versioning cache
- Gopal, Vijaykumar et al. - 1998
58
Parallel Computer Architecture (context) - Culler, Singh et al. - 1999
54
Piranha: A scalable architecture based on single-chip multip..
- Barroso, Gharachorloo - 2000
30
A chip multiprocessor architecture with speculative multithr..
- Krishnan, Torrellas - 1999
22
Simulation Analysis of Data Sharing in Shared Memory Multipr.. (context) - Eggers - 1989
22
SPEC CPU Benchmarks (context) - Evaluation - 1995
19
Language support for lightweight transactions
- Harris, Fraser - 2003
19
Speculative Lock Elision: enabling highly concurrent multith..
- Rajwar, Goodman - 2001
16
Transactional lock-free execution of lock-based programs
- Rajwar, Goodman - 2002
9
A class of compatible cache consistency protocols and their .. (context) - Sweazy, Smith - 1986
9
Transactional memory coherence and consistency (context) - Hammond, Wong et al. - 2004
8
Recent advances in memory consistency models for hardware sh..
- Adve, Pai et al. - 1999
7
Unbounded transactional memory (context) - Ananian, Asanovic - 2005
6
Spark98: Sparse matrix kernels for shared memory and message.. (context) - O'Hallaron - 1997
6
Technical report (context) - overview - 2003
6
Programming with transactional coherence and consistency (context) - Hammond, Carlstrom et al. - 2004
5
IEEE MICRO Magazine (context) - Hammond, Hubbert et al. - 2000
5
Virtualizing transactional memory (context) - Rajwar, Herlihy et al. - 2005
5
Simultaneous multi-threading implementation in POWER (context) - Kalla - 2003
4
Speculative synchronization: Applying thread-level speculati..
- Martinez, Torrellas - 2002
3
Coherence decoupling: Making use of incoherence
- Huh, Chang et al. - 2004
3
way multithreaded Sparc processor (context) - Kongetira - 2004
2
TAPE: A transactional application profiling environment
- Chafi, Minh et al. - 2005
2
Montecito: The next product in the Itanium Processor Family (context) - McNairy - 2004
2
Reordered speculative execution of critical sections
- Rundberg, Stenstrom - 2002
1
Tradeoffs in buffering multi-version memory state for specul.. (context) - Garzaran, Prvulovic - 2003
The graph only includes citing articles where the year of publication is known.
Documents on the same site (http://tcc.stanford.edu/publications/): More
Transactional Execution of Java Programs - Brian Carlstrom Jaewoong (2005)
(Correct)
The ATOMOS Transactional Programming Language - Carlstrom, McDonald, Chafi.. (2006)
(Correct)
ATLAS: A Scalable Emulator for Transactional Parallel Systems - Christos Kozyrakis And (2005)
(Correct)
Online articles have much greater impact More about CiteSeer.IST Add search form to your site Submit documents Feedback
CiteSeer.IST - Copyright Penn State and NEC