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Abstract: this paper, we use hardware counters to measure architectural features of a four-processor Pentium Probased server running a commercial database executing a TPC-C-like workload. We vary several hardware and firmware configuration parameters, such as L2 cache size, the number of processors and the number of outstanding bus transactions, to evaluate hardware design trade-offs. We examine the efficiency of caching, out-of-order execution, branch prediction, speculative execution, superscalar ... (Update)
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BibTeX entry: (Update)
@misc{ yong-kimberly,
author = "David Patterson Yong",
title = "Kimberly Keeton",
url = "citeseer.ist.psu.edu/736283.html" }
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