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Abstract: Current paper presents a hierarchical test pattern generation system that uses register-transfer level VHDL and gate-level EDIF netlist descriptions as inputs. The system includes appropriate interfaces to synthesize Decision Diagram (DD) models, a DD based test pattern generator and a fault simulator to evaluate the quality of the generated tests. In the paper, the structure of the system is presented. Additionally, representation of different design abstraction levels using decision... (Update)
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BibTeX entry: (Update)
G. Jervan, A. Markus, J. Raik, and R. Ubar, "DECIDER: A Decision Diagram based Hierarchical Test Generation System," Proc. Design & Diagnostics of Electronic Circuits & Systems Workshop, 1998, pp. 269--273. http://citeseer.ist.psu.edu/article/jervan98decider.html More
@misc{ jervan98decider,
author = "G. Jervan and A. Markus and J. Raik and R. Ubar",
title = "DECIDER: A Decision Diagram based Hierarchical Test Generation System",
text = "G. Jervan, A. Markus, J. Raik, and R. Ubar, DECIDER: A Decision Diagram
based Hierarchical Test Generation System, Proc. Design & Diagnostics of
Electronic Circuits & Systems Workshop, 1998, pp. 269--273.",
year = "1998",
url = "citeseer.ist.psu.edu/article/jervan98decider.html" }
Citations (may not include all citations):217 High-Level Synthesis: Introduction to Chip and System Design (context) - Gajski, Dutt et al. - 1992
143 HITEC: A test generation package for sequential circuits (context) - Niermann, Patel - 1991
50 Sequential circuit test generation in a genetic algorithm fr.. - Rudnick, Patel et al. - 1994
29 Test Synthesis with Alternative Graphs (context) - Ubar - 1996
21 Architectural level test generation for microprocessors (context) - Lee, Patel - 1994
20 Fast sequential circuit test generation using high-level and.. - Rudnick, Vietti et al. - 1998
19 Test Generation for Digital Circuits Using Alternative Graph.. (context) - Ubar - 1976
11 Hierarchical test generation under intensive global function.. (context) - Lee, Patel - 1992
5 Hierarchical Test Generation with Multi-Level Decision Diagr.. - Jervan, Markus et al. - 1998
2 Design Compiler Reference Manual Version (context) - Reference, Synopsys et al. - 1992
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