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Abstract: While architecture simulation is often treated as a methodology issue, it is at the core of most processor architecture research works, and simulation speed is often the bottleneck of the typical trialand -error research process. To speedup simulation during this research process and get trends faster, researchers usually reduce the trace size. More sophisticated techniques like trace sampling or distributed simulation are scarcely used because they are considered unreliable and complex due to... (Update)
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BibTeX entry: (Update)
@misc{ girbal-dist,
author = "Sylvain Girbal and Gilles Mouchard and Albert Cohen and Olivier Temam",
title = "DiST: A Simple, Reliable and Scalable Method to Significantly Reduce Processor
Architecture Simulation Time",
url = "citeseer.ist.psu.edu/article/girbal03dist.html" }
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A Polyhedral Approach to Ease the Composition of Program.. - Cohen, Girbal, Temam (2004) (Correct)
Putting Polyhedral Loop Transformations to Work - Bastoul, Cohen, Girbal.. (2003) (Correct)
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