Thesis Summary J. Gregory Steffan Thursday, Feb 27 2003, 2pm, Weh4623 Thesis...  Home/Search
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Abstract: Novel architectures that support multithreading, for example chip multiprocessors, have become increasingly commonplace over the past decade: examples include the Sun MAJC, IBM Power4, Alpha 21464, and Intel Xeon, HP PA-8800. However, only workloads composed of independent threads can take advantage of these processors---to improve the performance of a single application, that application must be transformed into a parallel version. Unfortunately the process of parallelization is extremely... (Update)
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BibTeX entry: (Update)
@misc{ gregory-hardware,
author = "Thesis Summary Gregory",
title = "Hardware Support for Thread-Level Speculation",
url = "citeseer.ist.psu.edu/733919.html" }
Citations (may not include all citations):251 Simultaneous Multithreading: Maximizing On-Chip Parallelism - Tullsen, Eggers et al. - 1995
222 The SGI Origin: A ccNUMA Highly Scalable Server (context) - Laudon, Lenoski - 1997
139 The Predictability of Data Values - Sazeides, Smith - 1997
125 Trace processors - Rotenberg, Jacobson et al. - 1997
117 Clock rate versus IPC: the end of the road for conventional .. - Agarwal, Hrishikesh et al. - 2000
116 Highly accurate data value prediction using hybrid predictor.. - Wang, Franklin - 1997
104 Lazy code motion - Knoop, Ruthing
103 Speculative execution based on value prediction - Gabbay, Mendelson - 1996
76 Doacross: Beyond vectorization for multiprocessors (context) - Cytron - 1986
72 A Dynamic Multithreading Processor - Akkary, Driscoll - 1998
53 High-speed multiprocessors and compilation techniques (context) - Padua, Kuck et al. - 1980
46 Quantifying the complexity of superscalar processors - Palacharla, Jouppi et al. - 1996
26 the value locality of store instructions - Lepak, Lipasti - 2000
24 Exceeding the dataflow limit via value prediction (context) - Lipasti, Shen - 1996
20 MAJC: Microprocessor Architecture for Java Computing (context) - Tremblay - 1999
19 Value prediction for speculative multithreaded architectures - Marcuello, Tubella et al. - 1999
18 Ev8: The post-ultimate alpha (context) - Emer - 2001
12 Power4: A Dual-CPU Processor Chip (context) - Kahle - 1999
11 A study of single-chip processor/ cache organizations for la.. - Farrens, Tyson et al. - 1994
10 Compiler optimization of scalar value communication between .. - Zhaia, Colohan et al. - 2002
8 Languages and Compilers for Parallel Computing (context) - Tjiang, Wolf et al. - 1992
3 Compiling sequential programs for a thread level speculative.. (context) - Colohan, Zhaia et al. - 2003
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