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Hardware Implementation of a Montgomery Modular Multiplier in a Systolic Array  (Make Corrections)  
Sddka Berna Örs, Lejla Batina, Bart Preneel, Joos Vandewalle



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Abstract: This paper describes a hardware architecture for modular multiplication operation which is efficient for bit-lengths suitable for both commonly used types of Public Key Cryptography (PKC) i.e. ECC and RSA Cryptosystems. The challenge of current PKC implementations is to deal with long numbers (160-2048 bits) in order to achieve system's efficiency, as well as security. RSA, still the most popular PKC, has at its root the modular exponentiation operation. Modular exponentiation consists of... (Update)

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BibTeX entry:   (Update)

@misc{ rs-hardware,
  author = "Sddka Berna Örs and Lejla Batina and Bart Preneel and Joos Vandewalle",
  title = "Hardware Implementation of a Montgomery Modular Multiplier in a Systolic
    Array",
  url = "citeseer.ist.psu.edu/731336.html" }
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2   Implementation of 1024-bit modular processor for RSA cryptos.. (context) - Kim, Kang et al. - 2000
2   Montgomery in practice: How to do it more efficiently in har.. (context) - Batina, Muurling - 2002
2   Systolic-arrays for modular exponentiation using Montgomery .. (context) - Iwamura, Matsumoto et al. - 1992

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