F. Dartu and L. Pileggi, "Calculating worse-case gate delays due to dominant capacitance coupling," in Proc. ACM/IEEE Design Automation Conf., 1997, pp. 46--51. (ResearchIndex)

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F. Dartu and L. Pileggi, "Calculating worse-case gate delays due to dominant capacitance coupling," in Proc. ACM/IEEE Design Automation Conf., 1997, pp. 46-51 (Make Corrections)
[8] C. Ebeling and B. Lockyear, "On the performance of level-clocked...

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Abstract: Recently, the electronic design automation industry has adopted the intellectual property (IP) business model as a dominant system-on-chip development platform. Since copyright fraud has been recognized as the most devastating obstruction to this model, a number of techniques for IP protection have been introduced. Most of them rely on a selection of a global solution to a design optimization problem according to a unique user-specific digital signature. Although such techniques provide strong... (Update)

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BibTeX entry: (Update)

@misc{ ebeling-dartu,
  author = "Ebeling And Lockyear",
  title = "F. Dartu and L. Pileggi, "Calculating worse-case gate delays due to dominant
    capacitance coupling," in Proc. ACM/IEEE Design Automation Conf., 1997,
    pp. 46--51.",
  url = "citeseer.ist.psu.edu/729416.html" }

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