H. Michael Ji Tensilica, Inc. Santa Clara, CA 95054  Home/Search
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Abstract: In this paper, we demonstrate how to design an optimized processor to achieve fast IP packet forwarding. By developing 2 customized instructions, we show how to achieve one routing lookup with 2 instructions compared with 100+ instructions with standard RISC processor. By using real routing table traces collected from backbone routers and packet traces, we show that we can achieve more than 10 million lookups per second (MLPS) in the worst case compared to 2 MLPS using general-purpose CPUs.... (Update)
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BibTeX entry: (Update)
@misc{ tensilica-fast,
author = "Michael Ji Tensilica",
title = "Fast Packet Forwarding with Configurable Processor",
url = "citeseer.ist.psu.edu/710243.html" }
Citations (may not include all citations):83 An Architecture for IP Address Allocation with CIDR (context) - Rekhter, Li - 1993
74 Small Forwarding Tables for Fast Routing Lookups - Degermark
60 Routing Lookups in Hardware at Memory Access Speeds - Gupta, Lin et al. - 1998
29 High-Performance IP Routing Table Lookup Using CPU Caching - Chiueh, Pradhan
6 A Novel IP-Routing Lookup Scheme and Hardware Architecture f.. (context) - Huang, Zhao - 1999
2 Fast IP Routing Lookup with 16/K and 16/Kc Compressed Data S.. (context) - Ji, Carchia - 2000
2 Fast IP Routing Lookup with Configurable Processor and Compr.. (context) - Ji, Srinivasan - 2000
1 Fast IP Packet Classification with Configurable Processor - Ji, Carchia - 2001
http://www.merit.edu/ipma/
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