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The Effect of Executing Mispredicted Load Instructions in a Speculative  (Make Corrections)  
Multithreaded Architecture Resit Sendag, Ying Chen, and David J. Lilja...



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Abstract: Concurrent multithreaded architectures exploit both instructionlevel and thread-level parallelism in application programs. A single-threaded sequencing mechanism needs speculative execution beyond conditional branches in order to exploit more instruction-level parallelism. In addition, an aggressive multithreaded architecture should also use thread-level control speculation in order to exploit more thread-level parallelism. The instructionand thread-level speculative execution of load... (Update)

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BibTeX entry:   (Update)

@misc{ resit-effect,
  author = "Multithreaded Architecture Resit",
  title = "The Effect of Executing Mispredicted Load Instructions in a Speculative",
  url = "citeseer.ist.psu.edu/706828.html" }
Citations (may not include all citations):
269   Multiscalar processors - Sohi, Breach et al. - 1995  ACM   DBLP
177   Evaluating future Microprocessors: The SimpleScalar Tool Set - Burger, Austin et al. - 1996
48   Speculative Precomputation: Long-range Prefetching of Delinq.. - Collins, Wang et al. - 2001  DBLP
37   Tolerating memory latency through software-controlled preexe.. - Luk - 2001
30   Wrong-Path Instruction Prefetching - Pierce, Mudge - 1996  ACM   DBLP
25   MinneSPEC: A New SPEC Benchmark Workload for Simulation-Base.. - KleinOsowski, Lilja - 2002
22   The Superthreaded Processor Architecture - Tsai, Huang et al. - 1999  ACM   DBLP
20   Performance Study of a Concurrent Multithreaded Processor - Tsai, Jiang et al. - 1998  ACM   DBLP
15   The potential for thread-level data speculation in tightly-c.. - Steffan, Mowry - 1997
12   The effect of speculative execution on cache performance (context) - Pierce, Mudge - 1994  ACM   DBLP
10   Measuring Computer Performance (context) - Lilja - 2000  ACM
5   The SImulator for Multithreaded Computer Architecture - Huang - 2000
4   Multithreaded Processors (context) - Ungerer, ad et al. - 2002  DBLP
4   Exploiting the Prefetching Effect Provided by Executing Misp.. - Sendag, Lilja et al. - 2002  ACM   DBLP

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Improving Processor Performance and Simulation Methodology - Yi   (Correct)

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