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Abstract: We present an Automatic Test Equipment architecture that is not limited by the number of pins it can serve. To achieve this, we introduce the idea of using Packet Switched Network as the mode of communication between ATE and the VLSI chip under test. We show that our architecture which we refer to as ZIP-ATE (Zero-to-Infinity Pin) reducesthe complexity and time involved in testing tens of chips at a time by a Multi-Site test philosophy. To increase the ATE utilization and available... (Update)
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BibTeX entry: (Update)
@misc{ nourani-zipate,
author = "Nourani And Vengatachalam",
title = "ZIP-ATE: Zero-to-Infinity Pins ATE Using Packet Switched Network",
url = "citeseer.ist.psu.edu/704020.html" }
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