See this document in CiteSeerX!

ZIP-ATE: Zero-to-Infinity Pins ATE Using Packet Switched Network  (Make Corrections)  
M. Nourani and S. Vengatachalam Center for Integrated Circuits Systems The...



  Home/Search   Context   Related

 
View or download:
utdallas.edu/~nourani/Res...fate_03.pdf
Cached:  PDF   PS.gz  PS  Image  Update  Help

From:  utdallas.edu/~nourani/Research... (more)
(Enter author homepages)

Rate this article: (best)
  Comment on this article  
(Enter summary)

Abstract: We present an Automatic Test Equipment architecture that is not limited by the number of pins it can serve. To achieve this, we introduce the idea of using Packet Switched Network as the mode of communication between ATE and the VLSI chip under test. We show that our architecture which we refer to as ZIP-ATE (Zero-to-Infinity Pin) reducesthe complexity and time involved in testing tens of chips at a time by a Multi-Site test philosophy. To increase the ATE utilization and available... (Update)

Active bibliography (related documents):   More   All
5.5:   TAN: A Packet Switched Network for VLSI Testing - Vengatachalam Nourani And   (Correct)
0.5:   Testing High-Speed SoCs Using Low-Speed ATEs - Mehrdad Nourani Center (2002)   (Correct)
0.3:   Recent Advances in Test Planning for Modular Testing .. - Iyengar.. (2002)   (Correct)

Similar documents based on text:   More   All
0.2:   RL-Huffman Encoding for Test Compression and Power.. - Nourani, Tehranipour (1995)   (Correct)
0.1:   OFDM: An Overview - Vengatachalam, al. (2002)   (Correct)
0.1:   Application of Fuzzy Logic in Resistive Fault Modeling.. - Nourani, Attarha, Lucas (2002)   (Correct)

BibTeX entry:   (Update)

@misc{ nourani-zipate,
  author = "Nourani And Vengatachalam",
  title = "ZIP-ATE: Zero-to-Infinity Pins ATE Using Packet Switched Network",
  url = "citeseer.ist.psu.edu/704020.html" }
Citations (may not include all citations):
29   Scan vector compression /decompression using statistical cod.. - Jas, Ghosh et al. - 1999
12   Essentials of Electronic Testing (context) - Bushnell, Agrawal - 2000
7   Test Economics for Multi-Site Test with Modern Cost Reductio.. (context) - Volkerink, Khoche et al. - 2002
4   Test Resource Optimization for Multi-Site Testing of SoCs Un.. (context) - Iyengar, Goel et al. - 2002
2   High-Speed Networks and Internets Performance and Quality of.. (context) - Stallings - 2002
2   Scan test data volume reduction in multi-clocked designs wit.. (context) - Jain, Waicukauski - 2002
2   Using Ethernet for Industrial I/O and Data Acquisition (context) - Potter - 1999
2   Testing High-Speed SoCs Using LowSpeed ATEs - Nourani, Chin - 2002
2   Transparent factories through industrial internets (context) - Swales, Gray - 1999
2   Test and Test Equipment (context) - Technology, Semiconductors - 1999
2   Data Network Design (context) - Spohn - 1997
2   Reducing test application time in high-level test generation (context) - Ravi, Lakshminarayana et al. - 2000
2   CSMACD Acces Method (context) - CD, http et al.
2   Test data compression for systemon -a-chip using Golomb code.. (context) - Chandra, Chakrabarty - 2000
2   A New Methodology for Improved Tester Utilization (context) - Khoche, Kapur et al. - 2001

Documents on the same site (http://www.utdallas.edu/~nourani/Research/signal_integrity/):   More
Detecting Signal-Overshoots for Reliability Analysis in.. - Nourani, Attarha (2002)   (Correct)
RL-Huffman Encoding for Test Compression and Power.. - Nourani, Tehranipour (1995)   (Correct)
Mixed RL-Huffman Encoding for Power Reduction and.. - Tehranipour..   (Correct)

Online articles have much greater impact   More about CiteSeer.IST   Add search form to your site   Submit documents   Feedback  

CiteSeer.IST - Copyright Penn State and NEC