Konrad Feyerabend  Home/Search
Context Related
| ses.informatik.unio...feyerabend96b.ps Cached: PS.gz PS PDF This document uses CoBlitz to cache paper downloads. If your firewall is blocking outgoing connections to port 3125, you can use these links to download local copies.
Image Update HelpPS.gz PS PDF From: ses.informatik.unioldenburg.d... (more) (Enter author homepages) |
Rate this article:      (best)Comment on this article |
Abstract: Symbolic Timing Diagrams [DJS95] have been introduced to increase acceptance of formal specification methods among hardware designers. Within the FORMAT project [KD96] they have been used as input language to automated verification tools. They have proven to be very valuable for easy to understand specifications of critical system requirements. Over the past few years, quantitative (real time) timing aspects have gained increasing attendance in formal specification and verification.... (Update)
Context of citations to this paper: More
...allow premature deactivation of the diagram. They are not used in the example and not considered in the rest of this paper. Refer to [9] for details. 2 Note that that target event of a leads to may well happen before the source event. No ordering is induced by a leads to...
...8, 16, 7] STD s may be compiled into first order temporal logic formulae which are then used for model checking. STD s are extended in [11, 10] to RTSTD s (Real time STD s) where a translation into a timed propositional temporal logic TPTL is provided. Both these research...
Cited by: More
Efficient Decompositional Model-Checking for Regular.. - Amla, Emerson, Namjoshi (1999) (Correct)
Verification of a Radio-Based Signaling System Using the.. - Damm, Klose (2001) (Correct)
A Visual Formalism for Real Time Requirement Specifications - Feyerabend, Josko (1997) (Correct)
Similar documents (at the sentence level):
43.1%: Real time Symbolic Timing Diagrams - Konrad Feyerabend Carl (Correct)
Active bibliography (related documents): More All
1.2: Real time Symbolic Timing Diagram - Feyerabend (1996) (Correct)
0.2: Hardware Synthesis from Requirement Specifications - Konrad Feyerabend Dept (Correct)
0.0: Verification of Automotive Control Units - Bienmüller, Bohn, Brinkmann.. (1999) (Correct)
Similar documents based on text: More All
0.6: Visual Temporal Logic as a Rapid Prototyping Tool - Fränzle, Lüth (2001) (Correct)
0.5: Compiling Graphical Real-Time Specifications into Silicon - Fränzle, Lüth (1998) (Correct)
0.5: The ICOS Synthesis Environment - Lüth (Correct)
Related documents from co-citation: More All
3: Specification and verification of VHDL-based system-level hardware designs (context) - Damm, Josko et al. - 1995
3: Really Visual Temporal Reasoning - Ramakrishna, Melliar-Smith et al. - 1993
3: A visual formalism for real time requirement specification - Feyerabend, Josko - 1997
BibTeX entry: (Update)
K. Feyerabend. Real time symbolic timing diagrams. Technical report, Department of Computer Science, Oldenburg University, September 1996. http://ca.informatik.uni-oldenburg.de. http://citeseer.ist.psu.edu/article/feyerabend96real.html More
@misc{ feyerabend96real,
author = "K. Feyerabend",
title = "Real time symbolic timing diagrams",
text = "K. Feyerabend. Real time symbolic timing diagrams. Technical report, Department
of Computer Science, Oldenburg University, September 1996. http://ca.informatik.uni-oldenburg.de.",
year = "1996",
url = "citeseer.ist.psu.edu/article/feyerabend96real.html" }
Citations (may not include all citations):404 Symbolic model checking for real-time systems - Henzinger, Nicollin et al. - 1994
268 The theory of timed automata - Alur, Dill - 1992
175 Logics and models of real time: A survey - Alur, Henzinger - 1992
172 A really temporal logic - Alur, Henzinger - 1994
29 Specification and verification of VHDL-based system-level ha.. (context) - Damm, Josko et al. - 1995
5 Formal Methods for Hardware Verification (context) - Kloos, Damm - 1996
2 Symbolic timing diagram specifications: getting started (context) - Josko - 1996
2 Graphical specification with real time symbolic timing diagr.. (context) - Feyerabend, Josko - 1996
1 Eine informelle Einfuhrung in Symbolische Zeitdiagramme (context) - Feyerabend - 1996
Documents on the same site (http://ses.informatik.uni-oldenburg.de/publications/): More
LSCs: Breathing Life into Message Sequence Charts - Damm, Harel (1998) (Correct)
Implementation of a New Weak Cache Coherence Protocol - Risau, Mikschl, Damm (Correct)
STATEMATE-based Rapid Prototyping Environment - Lüth, Metzner, Niehaus (Correct)
Online articles have much greater impact More about CiteSeer.IST Add search form to your site Submit documents Feedback
CiteSeer.IST - Copyright Penn State and NEC