Abstract:
Abstract — With power a major limiting factor in the design of scalable interconnected systems, power-aware networks will become inherent components of single-chip and multi-chip systems. As communication links consume significant power regardless of utilization, we propose and investigate power-aware networks whose links are turned on and off in response to bursts and dips in traffic. We explore the design space of such on/off networks, outlining a 5-step design methodology along with solutions at each step that can form the building blocks of numerous designs. Two specific designs targeting links with substantially different on/off times are then presented and evaluated. Our simulations show that up to 54.4 % power savings can be achieved along with at most 7.5 % increase in latency. I.
Citations
|
610
|
MediaBench: a Tool for Evaluating and Synthesizing Multimedia and Communicatons Systems
– Lee, Potkonjak, et al.
- 1997
|
|
258
|
Route packets, not wires: on-chip interconnection networks
– Dally, Toles
- 2001
|
|
206
|
The turn model for adaptive routing
– Glass, Ni
- 1994
|
|
65
|
1994.“Software Overhead in Messaging Layers: Where Does the Time
– Karamcheti, Chien
- 1994
|
|
37
|
The Alpha 21364 network architecture
– Mukerhjee, Bannon, et al.
- 2002
|
|
37
|
A Family of Fault-Tolerant Routing Protocols for Direct Multiprocessor Networks
– Gaughan, Yalamanchili
- 1995
|
|
33
|
Dynamic voltage scaling with links for power optimization of interconnection networks
– Shang, Peh, et al.
- 2003
|
|
32
|
C 'The Performance of Multicomputer Interconnection Networks', Computer
– Reed, Grunwald
- 1987
|
|
25
|
Myrinet: A gigabitper -second local area network
– Boden, Cohen, et al.
- 1995
|
|
21
|
Energy characterization of a tiled architecture processor with on-chip networks
– Kim, Taylor, et al.
- 2003
|
|
20
|
A theory of fault-tolerant routing in wormhole networks
– Duato
- 1998
|
|
20
|
A power-performance simulator for interconnection networks
– Wang, Zhu, et al.
- 2002
|
|
17
|
A variable-frequency parallel I/O interface with adaptive power-supply regulation
– Wei, Kim, et al.
- 2000
|
|
16
|
Optimal Fully Adaptive Wormhole Routing for Meshes
– Schwiebert, Jayasimha
- 1993
|
|
14
|
The Avici terabit switch/router
– Dally, Carvey, et al.
- 1998
|
|
12
|
Efficient on-chip global interconnects
– Ho, Mai, et al.
- 2003
|
|
7
|
Powering Networks on Chips: Energy-efficient and Reliable Interconnect Design for SoCs
– Benini, Micheli
- 2001
|
|
3
|
Energy optimization techniques
– Kim, Yum, et al.
- 2003
|
|
1
|
A 8Gbps on-chip serial link
– Jose, Patounakis, et al.
- 2003
|
|
1
|
Proof of deadlock-freedom for west-last east-last routing for on/off interconnection networks
– Soteriou
- 2004
|
