MetaCartSign in to MyCiteSeer

Include Citations | Advanced Search | Help

Include Citations | Advanced Search | Help

  Short Papers Estimation of Average Switching Activity in Combinational Logic Circuits Using Symbolic Simulation

Download:
Download as a PDF
by José Monteiro, Srinivas Devadas, Kurt Keutzer, Jacob White
http://tahoe.inesc-id.pt/pt/Ficheiros/1474.pdf
Add To MetaCart

Abstract:

Abstract—We address the problem of estimating the average switching activity of combinational circuits under random input sequences. Switching activity is strongly affected by gate delays, and for this reason we use a variable delay model in estimating switching activity. Unlike most probabilistic methods that estimate switching activity, our method takes into account correlation caused at internal gates in the circuit due to reconvergence of input signals. This method assumes a particular delay model and further assumes that the primary inputs to the combinational circuit are uncorrelated. Both these assumptions can be relaxed at the cost of increased complexity. We describe extensions to handle transmission gates and inertial delays in this paper. Index Terms—Power dissipation, probabilistic analysis, symbolic simulation. I.

Citations

2377 Graph-Based Algorithms for Boolean Function Manipulation – Bryant - 1986
296 Logic Minimization Algorithms for VLSI Synthesis – Brayton, McMullen, et al. - 1984
182 A survey of power estimation techniques in VLSI circuits – Najm - 1994
120 Transition Density: A New Measure of Activity in Digital Circuits – Najm - 1993
104 Built-In Test for VLSI Pseudorandom Techniques – Bardell, McAnney, et al. - 1987
80 Estimation of average switch activity in combinational and sequential circuits – Ghosh, Keutzer, et al. - 1992
67 The Design and Analysis of VLSI Circuits – Glasser, Dobberpuhl - 1985
33 Techniques for Power Estimation of Sequential Logic Circuits Under User-Specified Input – Monteiro, Devadas - 1994
28 Pattern-independent current estimation for reliability analysis of CMOS circuits – Burch, Najm, et al. - 1988
21 Estimation of maximum currents in MOS IC logic circuits – Chowdhury, Barkatullah - 1990
17 On the complexity of using bdds for the synthesis and analysis of boolean circuits – Chakravarty - 1989
9 Estimation of power dissipation – Devadas, Keutzer, et al. - 1990