See this document in CiteSeerX!

DLP + TLP Processors for the Next Generation of Media Workloads (2001)  (Make Corrections)  
Jesus Corbal, Roger Espasa and Mateo Valero Departament d'Arquitectura de...
HPCA



  Home/Search   Context   Related

 
View or download:
recerca.ac.upc.es/CA...jcorbal2001aC.ps
Cached:  PS.gz  PS  PDF   Image  Update  Help

From:  recerca.ac.upc....ublications2001 (more)
(Enter author homepages)

Rate this article: (best)
  Comment on this article  
(Enter summary)

Abstract: Future media workloads will require about two levels of magnitude the performance achieved by current general purpose processors. High uni-threaded performance will be needed to accomplish real-time constraints together with huge computational throughput, as next generation of media workloads will be eminently multithreaded (MPEG4 /MPEG-7). In order to fulfill the challenge of providing both good uni-threaded performance and throughput, we propose to join the simultaneous multithreading... (Update)

Similar documents based on text:   More   All
0.6:   On the Efficiency of Reductions in μ-SIMD Media Extensions - Corbal, Espasa, Valero (2001)   (Correct)
0.6:   Adding a Vector Unit to a Superscalar Processor - Quintana, Corbal, Espasa, Valero (1999)   (Correct)
0.6:   MOM: a Matrix SIMD Instruction Set Architecture for.. - Corbal, Espasa, Valero   (Correct)

BibTeX entry:   (Update)

@inproceedings{ corbal01dlp,
    author = "Jesus Corbal and Roger Espasa and Mateo Valero",
    title = "{DLP} + {TLP} Processors for the Next Generation of Media Workloads",
    booktitle = "{HPCA}",
    pages = "219-228",
    year = "2001",
    url = "citeseer.ist.psu.edu/699539.html" }
Citations (may not include all citations):
320   Mediabench: A tool for evaluating and synthesizing multimedi.. - Lee, Potkonjak et al. - 1997
186   Exploiting choice: Instruction fetch and issue on an impleme.. - Tullsen, Eggers et al. - 1996
135   MMX technology extension to the INTEL architecture (context) - Peleg, Weiser - 1996
68   How multimedia workloads will change processor design (context) - Diefendorff, Dubey - 1997
59   VIS speeds new media processing (context) - Tremblay, O'Connor et al. - 1996
54   Piranha: A Scalable Architecture Based on Single-Chip Multip.. - Barroso, Gharachorloo et al. - 2000
32   A new direction for computer architecture research - Kozyrakis, Patterson - 1998
23   Simultaneous Multithreading: Multiplying Alpha's Performance (context) - Emer - 1999
22   Simple Vector Microprocessors for Multimedia Applications - Lee, Stoodley - 1998
21   Altivec extension to powerPC accelerates media processing (context) - Diefendorff, Dubey - 2000
16   Power4 Focuses on Memory Bandwidth (context) - Diefendorff - 1999
16   University of California at Berkeley (context) - Asanovic, Phd - 1998
16   Exploiting a new level of DLP in multimedia applications - Corbal, Espasa et al. - 1999
13   Alpha 21364: A Scalable Single-chip SMP (context) - Bannon - 1998
10   Performance estimation of multistreamed (context) - Yamamoto, Serrano et al. - 1994
10   Vector unit architecture for emotion synthesis (context) - Kunimatsu, Ide et al. - 2000
9   Exploiting Instruction- and Data- Level Parallelism - Espasa, Valero - 1997
7   Tomorrow's computing engines (context) - Dally - 1998
7   multimedia for our time (context) - Koenen - 1999
6   Adding a vector unit on a superscalar processor (context) - Quintana, Corbal et al. - 1999
4   Out-of-order execution may not be cost effective on processo.. (context) - Hily, Seznec - 1999
4   MPEG-2 video decompression on simultaneous multithreaded mul.. - Oehring, Sigmund et al. - 1999
4   Technical Report httpwww (context) - for, with et al. - 1997
3   Challenges to combine general-purpose and multimedia process.. (context) - Conte - 1997
3   Advanced Micro Devices (context) - technology, http et al. - 1999
1   Motion video instructions (context) - Weiss, Hicks - 1999
1   Simultameous multithreading: Maximizing on-chip parallelism (context) - Tullsen, Eggers et al. - 1995
1   Applying and implementing the MPEG-4 multimedia standard (context) - Kneip, Schmale et al. - 1999

Documents on the same site (http://recerca.ac.upc.es/CAP/hpc/HPC-Publications2001.html):   More
Load Redundancy Elimination on Executable Code - Fernández, Espasa, Debray   (Correct)
Modulo Scheduling with Integrated Register Spilling - For Clustered Vliw (2001)   (Correct)
On the Potential of Tolerant Region Reuse for Multimedia - Applications Carlos Alvarez (2001)   (Correct)

Online articles have much greater impact   More about CiteSeer.IST   Add search form to your site   Submit documents   Feedback  

CiteSeer.IST - Copyright Penn State and NEC