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Abstract: Large instruction window processors achieve high performance by exposing large amounts of instruction level parallelism. However, accessing large hardware structures typically required to buffer and process such instruction window sizes significantly degrade the cycle time. This paper proposes a novel Checkpoint Processing and Recovery (CPR) microarchitecture, and shows how to implement a large instruction window processor without requiring large structures thus permitting a high clock... (Update)
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0.7: Adrin Cristal - Jos Martnez Josep (2003) (Correct)
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BibTeX entry: (Update)
@misc{ large-checkpoint,
author = "Towards Scalable Large",
title = "Checkpoint Processing and Recovery:",
url = "citeseer.ist.psu.edu/693742.html" }
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7 The Alpha 21264: A 500 MHz out-of-order execution microproce.. (context) - Leibholz, Razdan - 1997
6 Hierarchical scheduling windows (context) - Brekelbaum, Wilkerson et al. - 2002
5 Large virtual ROBs by processor checkpointing (context) - Cristal, Valero et al. - 2002
5 A day in the life of a data cache miss - Karkhanis, Smith - 2002
4 Cherry: Checkpointed early resource recycling in out-of-orde.. (context) - Martnez, Renau et al. - 2002
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