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Abstract: Fault diagnosis is to predict the potential fault sites in a logic IC. In this paper, we particularly address the problem of diagnosing faults that exhibit the so-called Byzantine General's phenomenon, in which a fault manifests itself as a non-logical voltage level at the fault site. Previously, explicit enumeration was suggested to deal with such a problem. However, it is often too time-consuming because the CPU time is exponentially proportional to fanout degree of the circuit under... (Update)
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BibTeX entry: (Update)
@misc{ huang-symbolic,
author = "Shi-Yu Huang",
title = "A Symbolic Inject-and-Evaluate Paradigm for Byzantine Fault Diagnosis",
url = "citeseer.ist.psu.edu/689969.html" }
Citations (may not include all citations):1726 Graph-based Algorithms for Boolean Function Manipulation - Bryant - 1986
308 Digital System Testing and Testable Design (context) - Abramovici, Breuer et al. - 1990
17 Diagnosis and Correction of Logic Design Errors in Digital C.. (context) - Chung, Wang et al. - 1993
9 ErrorTracer: A Fault Simulation Based Approach to Design Err.. (context) - Huang, Cheng et al. - 1997
7 Multiple Error Diagnosis Based On Xlists (context) - Boppana, Mukherjee et al. - 1999
4 SIS: A System for Sequential Circuit Synthesis (context) - Brayton - 1992
3 On Improving The Accuracy of Multiple Fault Diagnosis (context) - Huang - 2001
2 Modelling the Unmodellable: Algorithmic Fault Diagnosis (context) - Aitken - 1996
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