(Enter summary)
Abstract: Interchip I/O bandwidth is a critical bottleneck in VLSI systems. To
make the best use of this resource the conventions and circuits used for
inter-chip signaling must be optimized to achieve the maximum bit rate
with minimumpower dissipation. This paper describes a set of I/O pads
that we have developed at MIT. They operate with small signal levels
to reduce power dissipation. To achieve high bandwidth, they operate
simultaneously in both directions over a single wire and are isolated
from... (Update)
Context of citations to this paper: More
...single point of failure in the clock net. The RR solves the high pinout problem by using current mode simultaneous bidirectional signalling [6]. This method has reduced the chip signal pin count from 311 signal pins to 215. This is a saving of 96 signal pins over a conventional...
...a very small fraction of link bandwidth. The RR solves the high pinout problem by using current mode simultaneous bidirectional signalling [6]. This method has yielded a saving of 92 signal pins over a conventional signalling mechanism. 2 Architectural Overview The Reliable...
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BibTeX entry: (Update)
L. R. Dennison, W. S. Lee, and W. J. Dally. High performance bidirectional signalling in VLSI systems. Proceedings of the 1993 Symposium of Research on Integrated Systems, 1993. http://citeseer.ist.psu.edu/67699.html More
@misc{ dennison93high,
author = "L. Dennison and W. Lee and W. Dally",
title = "High performance bidirectional signalling in VLSI systems",
text = "L. R. Dennison, W. S. Lee, and W. J. Dally. High performance bidirectional
signalling in VLSI systems. Proceedings of the 1993 Symposium of Research
on Integrated Systems, 1993.",
year = "1993",
url = "citeseer.ist.psu.edu/67699.html" }
Citations (may not include all citations):
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low power cmos transmitter-receiver system (context) - Gabara, Thompson - 1988
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