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Abstract: We present a framework that considers global routing, repeater insertion, and flip-flop relocation for early interconnect planning. We formulate the interconnect retiming and flip-flop placement problem as a local area constrained retiming problem and solve it as a series of weighted minimum area retiming problems. Our method for early interconnect planning can reduce and even avoid design iterations between physical planning and high level designs. Experimental results show that our method can ... (Update)
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BibTeX entry: (Update)
@misc{ and-interconnect,
author = "Ruibing Lu And",
title = "Interconnect Planning with Local Area Constrained Retiming",
url = "citeseer.ist.psu.edu/676912.html" }
Citations (may not include all citations):207 Retiming synchronous circuitry (context) - Leiserson, Saxe - 1991 DBLP
76 Will physical scalability sabotage performance gains - Matzke - 1997
33 Buffer block planning for interconnect-driven floorplanning - Cong, Kong et al. - 1999 ACM DBLP
22 Efficient implementation of retiming - Shenoy, Rudell - 1994 ACM
22 New algorithms for the rectilinear Steiner tree problem (context) - Ho, Vijayan et al. - 1990
15 Routability-driven repeater block planning for interconnect-.. - Sarkar, Koh - 2000 ACM DBLP
13 Provably good global buffering using an available buffer blo.. - Dragan, Kahng et al. - 2000 ACM DBLP
11 An improved algorithm for minimum-area retiming - Maheshwari, Sapatnekar - 1997 ACM DBLP
9 A practical methodology for early buffer and wire resource a.. (context) - Alpert, Hu et al. - 2001 ACM DBLP
3 Flip-flop and repeater insertion for early interconnect plan.. - Lu, Zhong et al. - 2002 ACM DBLP
3 Integration of retiming with architectural floorplanning - Tabara, Tabbara et al. - 2000 ACM DBLP
3 Repeater block planning under simultaneous delay and transit.. - Sarkar, Koh - 2001 ACM DBLP
2 Performance planning (context) - Otten, Brayton - 2000 ACM DBLP
1 Interconnect tuning strategies for global interconnects in h.. (context) - Dragan, Muddu et al. - 1998
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