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Modeling and Optimization of VLSI Interconnects (1999)  (Make Corrections)  (1 citation)
Lei He
Lecture Notes in Computer Science



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Abstract: of the Dissertation University of California, Los Angeles, 1999 Professor Jason Cong, Chair As very large scale integrated (VLSI) circuits move into the era of deepsubmicron (DSM) technology and gigahertz frequency, the system performance has increasingly become dominated by the interconnect delay. This dissertation presents five related research topics on interconnect layout optimization, and interconnect extraction and modeling: the multi-source wire sizing (MSWS) problem, the... (Update)

Context of citations to this paper:   More

.... table, EFP stands for the effective fringing property based algorithm in [22] STIS for the extended local refinement based algorithm in [37, 36], and GISS for our bound refinement based algorithm as in Section 4, respectively, for computing lower and upper bounds, then...

Cited by:   More
Interconnect Sizing and Spacing with Consideration of.. - Cong, He, Koh, Zhigang (2001)   (Correct)

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26.5%:   Modeling and Optimization of VLSI Interconnects - He (1999)   (Correct)
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1.0:   Interconnect Performance Estimation Models for Design Planning - Cong, Pan (2001)   (Correct)

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2:   Global interconnect sizing and spacing with consideration of coupling capacitanc.. - Cong, He et al. - 1997
2:   Optimal wiresizing under the distributed Elmore delay model - Cong, Leung - 1993

BibTeX entry:   (Update)

L. He, Modeling and Optimization of VLSI Interconnects. PhD thesis, University of California, Los Angeles, 1999. http://citeseer.ist.psu.edu/article/he99modeling.html   More

@article{ he99modeling,
    author = "Yong He and Ishfaq Ahmad and Ming L. Liou",
    title = "Modeling and Scheduling for {MPEG}-4 Based Video Encoder Using a Cluster of Workstations",
    journal = "Lecture Notes in Computer Science",
    volume = "1557",
    pages = "306--316",
    year = "1999",
    url = "citeseer.ist.psu.edu/article/he99modeling.html" }
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Documents on the same site (http://eda.ee.ucla.edu/pub/):   More
Interconnect Design for Deep Submicron ICs - Cong, Pan, He, Koh, Khoo (1997)   (Correct)
Vector Potential Equivalent Circuit Based on PEEC Inversion - Yu, He (2003)   (Correct)
Integrity-driven Power and Signal Network Codesign - Jinjun Xiong And   (Correct)

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