Silviu Ciricescu, Ray Essick, Brian Lucas, Phil May, Kent Moat, Jim Norris, Michael Schuette, Ali Saidi  Home/Search
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Abstract: The need to process multimedia data places large computational demands on portable/embedded devices. These multimedia functions share common characteristics: they are computationally intensive and data-streaming, performing the same operation(s) on many data elements. The Reconfigurable Streaming Vector Processor (RSVP ) is a vector coprocessor architecture that accelerates streaming data operations. Programming the RSVP architecture involves describing the shape and location of vector... (Update)
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BibTeX entry: (Update)
@misc{ ciricescu-reconfigurable,
author = "Silviu Ciricescu and Ray Essick and Brian Lucas and Phil May and Kent Moat
and Jim Norris and Michael Schuette and Ali Saidi",
title = "The Reconfigurable Streaming Vector Processor (RSVP™)",
url = "citeseer.ist.psu.edu/671115.html" }
Citations (may not include all citations):210 Synchronous data flow (context) - Lee, Messerschmitt - 1987
135 MMX Technology Extension to the Intel Architecture (context) - Peleg, Weiser - 1996
54 Scalable processors in the billion-transistor era: IRAM - Kozyrakis, Perissakis et al. - 1997
23 PipeRench: A Reconfigurable Architecture and Compiler - Goldstein, Schmit et al. - 2000
21 The Cray-1 Computer System (context) - Russell - 1978
17 Intel's MMX speeds multimedia (context) - Gwennap - 1996
6 Cost-effective Hardware Acceleration of Multimedia Applicati.. - Talla, John - 2001
4 The Memory Gap and the Future of HighPerformance Memories (context) - Wilkes - 2001
4 The Imagine Stream Processor - Kapasi, Dally et al. - 2002
3 Control Data STAR-100 processor design (context) - Hintz, Tate - 1972
3 Vector Microprocessors for Desktop Computing - Stoodley, Lee - 1998
3 An Introduction to Vector Processing (context) - Johnson - 1978
3 G4 is First PowerPC with AltiVec (context) - Gwennap - 1998
3 The Best Way to Achieve Vector-Like Performance (context) - Smith - 1994
2 Cray X-MP: The Birth of a Supercomputer (context) - August, Brost et al. - 1989
1 AltiVec Extension to PowerPC Accelerates Multimedia Processi.. (context) - Diefendorff, Dubey et al. - 2000
1 AltivecTM Technology Programming Environments Manual (context) - Semiconductor - 1998
1 Intel Wireless MMX Technology (context) - Paver - 2002
1 The ARM Architecture Version 6 (context) - Brash - 2002
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