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Abstract: To date all the proposals for low power designs of RAMs essentially focus on circuit level solutions. What we propose here is a novel architecture (high) level solution. Our methodology provides a systematic tradeoff between power and area. Also, it allows tradeoff between test time and power consumed in test mode. Significantly, too, the proposed design has the potential to achieve performance improvements while simultaneously reducing power. In this respect it stands apart from other... (Update)
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BibTeX entry: (Update)
@misc{ bhattacharjee-lpram,
author = "Subhasis Bhattacharjee and Dhiraj K. Pradhan",
title = "LPRAM: A Novel Low Power RAM Design with Testability",
url = "citeseer.ist.psu.edu/670062.html" }
Citations (may not include all citations):159 Principles of CMOS VLSI Design : a systems perspective (context) - Weste, Eshraghian - 1992
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3 Trends in megabit DRAM circuit design (context) - Itoh - 1990
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2 Power reduction in megabit DRAM's (context) - Kimura - 1986
2 A Low Power RAM Design (context) - Bhattacharjee, Pradhan et al. - 2003
1 Half-CDED bit-line sensing scheme in CMOS DRAM (context) - Lu, Chao - 1984
1 Semiconductor Memories - Technology, Testing and Reliability (context) - Sharma - 1997
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