Decoupled Pipelines: Rationale, Analysis, and Evaluation
Abstract:
This paper analyzes the potential of asynchronous, decoupled pipelines from an architectural viewpoint. Previous work in this area has been implementation oriented and has concentrated on developing circuit models and design tools needed to actually build a simple clockless processor. This past work has shown that asynchronous processing is a viable approach, with several inherent advantages over synchronous processing. This paper breaks from this implementation focus and instead considers what is gained architecturally when the globally synchronous clock is removed. We first present the design of a decoupled, self-timed asynchronous architecture in which each pipeline component is able to determine its own operating speed. Our design includes micropipelines between stages to provide extra elasticity, allowing the pipeline to dynamically adjust to long latency operations. We then show how this organization enables a new style of prediction-based optimizations that is not possible in a synchronous processor. Finally, we provide preliminary results of a complete VHDL simulator which demonstrate that these optimizations can carry a significant performance advantage. 1
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| 1 | Graphics Corporation. Renoir Version 99.1 (Build 26 – Mentor |
